Program Disturb Improvements in Multi-Tier Memory Devices Including Improved Non-Data Conductive Gate Implementation

    公开(公告)号:US20210257035A1

    公开(公告)日:2021-08-19

    申请号:US16791253

    申请日:2020-02-14

    Abstract: Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier comprising a first plurality of memory cells and the upper tier comprising a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.

    Non-volatile memory with countermeasure for program disturb including delayed ramp down during program verify

    公开(公告)号:US10541037B2

    公开(公告)日:2020-01-21

    申请号:US16002793

    申请日:2018-06-07

    Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

    Non-volatile memory with early dummy word line ramp down after precharge

    公开(公告)号:US12112812B2

    公开(公告)日:2024-10-08

    申请号:US17884929

    申请日:2022-08-10

    CPC classification number: G11C16/3427 G11C16/0483 G11C16/10

    Abstract: Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected data word line after the pre-charging and applying a program voltage pulse to selected non-volatile memory cells connected to the selected data word line while boosting. The pre-charging includes applying pre-charge voltages to one set of data word lines and dummy word line(s) as well as applying overdrive voltages to another set of data word lines connected to already programmed memory cells. At the end of the pre-charging, the dummy word lines are ramped down to a resting voltage prior to lowering the data word lines to one or more resting voltages.

    NON-VOLATILE MEMORY WITH TIER-WISE RAMP DOWN AFTER PROGRAM-VERIFY

    公开(公告)号:US20240071529A1

    公开(公告)日:2024-02-29

    申请号:US17898850

    申请日:2022-08-30

    CPC classification number: G11C16/3459 G11C16/0433 G11C16/08 G11C16/102

    Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

    MEMORY DEVICE THAT IS OPTIMIZED FOR OPERATION AT DIFFERENT TEMPERATURES

    公开(公告)号:US20230162809A1

    公开(公告)日:2023-05-25

    申请号:US17533292

    申请日:2021-11-23

    CPC classification number: G11C16/3459 G11C16/0483 G11C16/10 G11C16/26

    Abstract: A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

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