公开(公告)号：US11239204B2

公开(公告)日：2022-02-01

申请号：US16694400

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.

公开(公告)号：US11164883B2

公开(公告)日：2021-11-02

申请号：US16019904

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani ,  Jayavel Pachamuthu

IPC: H01L27/11582 ,  G11C8/14 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US11074976B2

公开(公告)日：2021-07-27

申请号：US16551553

申请日：2019-08-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  G11C16/14 ,  G11C16/30 ,  H03H11/28 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

公开(公告)号：US10991721B2

公开(公告)日：2021-04-27

申请号：US16886081

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Raghuveer S. Makala ,  Masaaki Higashitani

IPC: H01L29/76 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L27/11524 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US10950311B2

公开(公告)日：2021-03-16

申请号：US16456036

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US10923196B1

公开(公告)日：2021-02-16

申请号：US16781589

申请日：2020-02-04

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  H01L27/06 ,  G11C16/34

Abstract: An apparatus for erasing non-volatile storage elements in a non-volatile memory system is disclosed. The apparatus has consistent speed in gate induced drain leakage (GIDL) erase across the operating temperature of the memory system. In one aspect, a voltage source outputs an erase voltage to NAND strings. The NAND strings may draw a GIDL erase current in response to the erase voltage. The amount of GIDL erase current for a given erase voltage is highly temperature dependent. The GIDL erase current may be sampled, and the erase voltage regulated based on the GIDL erase current. Therefore, the GIDL erase current, as well as erase speed, may be kept uniform across operating temperatures.

公开(公告)号：US10825827B2

公开(公告)日：2020-11-03

申请号：US16141149

申请日：2018-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mohan Dunga ,  James Kai ,  Venkatesh P. Ramachandra ,  Piyush Dak ,  Luisa Lin ,  Masaaki Higashitani

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11573 ,  G11C7/10 ,  G11C16/10 ,  G11C16/28 ,  H01L27/1157

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.

公开(公告)号：US10763271B2

公开(公告)日：2020-09-01

申请号：US16019961

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani ,  Jayavel Pachamuthu

IPC: H01L27/11 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US10650898B1

公开(公告)日：2020-05-12

申请号：US16182031

申请日：2018-11-06

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11524

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.

公开(公告)号：US20200013714A1

公开(公告)日：2020-01-09

申请号：US16168232

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11582 ,  H01L49/02

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.