公开(公告)号：US20140179067A1

公开(公告)日：2014-06-26

申请号：US14190635

申请日：2014-02-26

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L29/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

Abstract translation: 公开了半导体封装及其制造方法。 该制造方法包括以下步骤：提供具有与活性表面相对的活性表面和非活性表面的半导体芯片，粗糙化非活性表面的周边部分，以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分，通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上，在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合，并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。

公开(公告)号：US12255182B2

公开(公告)日：2025-03-18

申请号：US18235079

申请日：2023-08-17

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Meng-Huan Chia ,  Yih-Jenn Jiang ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/16

Abstract: An electronic package is provided, in which a first electronic element and a second electronic element are disposed on a first side of a circuit structure and a second side of the circuit structure, respectively, where a first metal layer is formed between the first side of the circuit structure and the first electronic element, a second metal layer is formed on a surface of the second electronic element, and at least one thermally conductive pillar is disposed on the second side of the circuit structure and extends into the circuit structure to thermally conduct the first metal layer and the second metal layer. Therefore, through the thermally conductive pillar, heat generated during operations of the first electronic element and the second electronic element can be quickly dissipated to an external environment and would not accumulate.

公开(公告)号：US12100642B2

公开(公告)日：2024-09-24

申请号：US17854241

申请日：2022-06-30

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Yuan-Hung Hsu

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/433

CPC classification number: H01L23/433 ,  H01L21/4871 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29194 ,  H01L2224/32245

Abstract: An electronic package is provided and includes an electronic element, an intermediary structure disposed on the electronic element, and a heat dissipation element bonded to the electronic element through the intermediary structure. The intermediary structure has a flow guide portion and a permanent fluid combined with the flow guide portion so as to be in contact with the electronic element, thereby achieving a preferred heat dissipation effect and preventing excessive warping of the electronic element or the heat dissipation element due to stress concentration.

公开(公告)号：US12080618B2

公开(公告)日：2024-09-03

申请号：US17583946

申请日：2022-01-25

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Kuo-Hua Yu ,  Chang-Fu Lin

IPC: H01L23/48 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29109 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/32221 ,  H01L2924/0635

Abstract: A heat dissipation structure is provided and includes a heat dissipation body and an adjustment channel. A carrying area and an active area adjacent to the carrying area are defined on a surface of the heat dissipation body, the carrying area is used for applying a first heat dissipation material thereonto, and the adjustment channel is formed in the active area, where one end of the adjustment channel communicates with the outside of the heat dissipation structure, and the other end communicates with the carrying area. Therefore, when the heat dissipation body is coupled to the electronic component by the first heat dissipation material, the adjustment channel can adjust a volume of the first heat dissipation material.

公开(公告)号：US11676948B2

公开(公告)日：2023-06-13

申请号：US17337752

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kong-Toon Ng ,  Hung-Ho Lee ,  Chee-Key Chung ,  Chang-Fu Lin ,  Chi-Hsin Chiu

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/24153 ,  H01L2224/73209 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.

公开(公告)号：US11605554B2

公开(公告)日：2023-03-14

申请号：US17392462

申请日：2021-08-03

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chih-Ming Huang ,  Kuo-Hua Yu ,  Chang-Fu Lin

IPC: H01L21/68 ,  H01L23/00 ,  H01L21/683

Abstract: A flip-chip process is to provide a pressing jig with a channel, so that the pressing jig grips a chip module by vacuum suction through the channel, and the chip module can be bonded onto a circuit board via a plurality of solder bumps through the pressing jig, and then a heating device is provided to heat the plurality of solder bumps and reflow the plurality of solder bumps. Therefore, the chip module can be vacuum-gripped by the pressing jig to suppress deformation of the chip module, so that the solder bumps can effectively connect to corresponding contacts of the circuit board.

公开(公告)号：US11532528B2

公开(公告)日：2022-12-20

申请号：US17160720

申请日：2021-01-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Don-Son Jiang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.

公开(公告)号：US11516925B2

公开(公告)日：2022-11-29

申请号：US16856259

申请日：2020-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Han-Hung Chen ,  Yuan-Hung Hsu ,  Chang-Fu Lin ,  Rung-Jeng Lin ,  Fu-Tang Huang

IPC: H05K3/46 ,  H01L21/02 ,  H05K3/34 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00 ,  H05K1/18 ,  H05K3/00 ,  H01L23/31 ,  H01L23/538

Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

公开(公告)号：US20220148975A1

公开(公告)日：2022-05-12

申请号：US17134925

申请日：2020-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wei-Jhen Chen ,  Chih-Hsun Hsu ,  Yuan-Hung Hsu ,  Chih-Nan Lin ,  Chang-Fu Lin ,  Don-Son Jiang ,  Chih-Ming Huang ,  Yi-Hsin Chen

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

公开(公告)号：US11101566B2

公开(公告)日：2021-08-24

申请号：US16928289

申请日：2020-07-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Han-Hung Chen ,  Chun-Yi Huang ,  Chang-Fu Lin ,  Rung-Jeng Lin ,  Kuo-Hua Yu

IPC: H01Q9/04 ,  H05K1/14 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H01Q1/22 ,  H05K3/36

Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.