公开(公告)号：US20190273054A1

公开(公告)日：2019-09-05

申请号：US16295727

申请日：2019-03-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Hsin Chen ,  Chia-Hsin Wu ,  Po-Yi Wu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A substrate structure and a method for fabricating the same are provided. A barrier layer is formed on an entire top surface of a wiring layer of a substrate body to isolate the wiring layer from moisture and prevent the wiring layer from being oxidized. Therefore, the wiring layer is securely bonded to an insulation layer, thereby preventing the delamination or peeling problem from occurring.

公开(公告)号：US20220148975A1

公开(公告)日：2022-05-12

申请号：US17134925

申请日：2020-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wei-Jhen Chen ,  Chih-Hsun Hsu ,  Yuan-Hung Hsu ,  Chih-Nan Lin ,  Chang-Fu Lin ,  Don-Son Jiang ,  Chih-Ming Huang ,  Yi-Hsin Chen

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

公开(公告)号：US08569162B2

公开(公告)日：2013-10-29

申请号：US13644006

申请日：2012-10-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Feng-Lung Chien ,  Yi-Hung Lin ,  Yi-Hsin Chen

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/15788 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/0231 ,  H01L2924/00

Abstract: A conductive bump structure is formed on a substrate having a plurality of bonding pads and a first insulating layer thereon. The first insulating layer has a plurality of openings formed therein for exposing the bonding pads and a conductive post is formed on the bonding pads exposed through the openings. Therein, a gap is formed between the conductive post and the wall of the opening such that no contact occurs between the conductive post and the first insulating layer, thereby preventing delamination of the conductive bump structure caused by stresses concentrating on an interface of different materials as in the prior art.

Abstract translation: 在具有多个接合焊盘的基板上形成导电凸块结构，在其上具有第一绝缘层。 第一绝缘层具有形成在其中的多个开口用于暴露接合焊盘，并且在通过开口暴露的接合焊盘上形成导电柱。 其中，在导电柱和开口壁之间形成间隙，使得在导电柱和第一绝缘层之间不会发生接触，从而防止由于集中在不同材料的界面上的应力引起的导电凸块结构的分层，如 在现有技术中。

公开(公告)号：US20230361091A1

公开(公告)日：2023-11-09

申请号：US18220501

申请日：2023-07-11

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wei-Jhen Chen ,  Chih-Hsun Hsu ,  Yuan-Hung Hsu ,  Chih-Nan Lin ,  Chang-Fu Lin ,  Don-Son Jiang ,  Chih-Ming Huang ,  Yi-Hsin Chen

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L21/565 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/81801 ,  H01L2924/182 ,  H01L2224/73204

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

公开(公告)号：US11742296B2

公开(公告)日：2023-08-29

申请号：US17134925

申请日：2020-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wei-Jhen Chen ,  Chih-Hsun Hsu ,  Yuan-Hung Hsu ,  Chih-Nan Lin ,  Chang-Fu Lin ,  Don-Son Jiang ,  Chih-Ming Huang ,  Yi-Hsin Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: An electronic package and a manufacturing method thereof, which embeds an electronic structure acting as an auxiliary functional component and a plurality of conductive pillars in an encapsulation layer, and disposes an electronic component on the encapsulation layer, so as to facilitate electrical transmission with the electronic component in a close range.

公开(公告)号：US20150072517A1

公开(公告)日：2015-03-12

申请号：US14487413

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/0347 ,  H01L2224/1161 ,  H01L2224/05552

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Abstract translation: 半导体结构的制造方法包括提供至少具有电极焊盘的芯片，在电极焊盘上形成钛层，在芯片上形成电介质层和钛层的一部分，在电介质层上形成铜层 和钛层，在与铜层相对应的铜层上形成导电柱，并除去未被导电柱覆盖的铜层的一部分。 当通过蚀刻去除铜层的部分时，由于钛层被电介质层覆盖，所以避免了钛层的底切，从而为导电柱提供改进的支撑以提高产品的可靠性。