公开(公告)号：US20150155025A1

公开(公告)日：2015-06-04

申请号：US14297336

申请日：2014-06-05

Applicant: SK hynix Inc.

Inventor： Jae-Seung LEE ,  Choung-Ki SONG

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40611

Abstract: A semiconductor memory device includes a normal command generation unit suitable for generating a normal refresh command in response to a refresh command; a smart command generation unit suitable for performing a counting operation on the refresh command to generate a plurality of smart refresh commands which are activated at a predetermined period; and a refresh operation unit suitable for performing a refresh operation in response to the normal refresh command and the plurality of smart refresh commands, wherein the smart command generation unit resets the counting operation when entering into the refresh operation.

Abstract translation: 半导体存储器件包括：适于根据刷新命令生成正常刷新命令的正常命令生成单元; 智能命令生成单元，其适于对所述刷新命令进行计数操作，以生成在预定周期被激活的多个智能刷新命令; 以及适用于响应于正常刷新命令和多个智能刷新命令执行刷新操作的刷新操作单元，其中智能命令生成单元在进入刷新操作时复位计数操作。

公开(公告)号：US20150155023A1

公开(公告)日：2015-06-04

申请号：US14293649

申请日：2014-06-02

Applicant: SK hynix Inc.

Inventor： Yo-Sep LEE ,  Chang-Hyun KIM ,  Choung-Ki SONG

IPC: G11C8/18 ,  G11C8/06 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C8/18

Abstract: A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.

Abstract translation: 半导体存储器件包括：时钟信号生成单元，适于分割外部时钟信号以产生对应于外部时钟信号的奇数周期的第一内部时钟信号和对应于偶数周期的第二内部时钟;第一输入单元， 用于响应于第一内部时钟信号接收外部命令信号和外部地址信号，第二输入单元适于响应于第二内部时钟信号接收外部命令信号和外部地址信号;以及操作控制单元 适于在减速模式期间启用第一输入单元和第二输入单元中的一个并禁用第一输入单元和第二输入单元中的另一个。

公开(公告)号：US20150149820A1

公开(公告)日：2015-05-28

申请号：US14192531

申请日：2014-02-27

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G06F11/20

CPC classification number: G06F11/1441 ,  G06F11/1456 ,  G06F11/2002 ,  G06F11/2005 ,  G06F11/2007 ,  G06F11/201 ,  G06F11/2017

Abstract: A memory unit including a first data transferring/receiving unit suitable for transferring/receiving data through a first data bus for communication with a host, a second data transferring/receiving unit suitable for transferring/receiving data through a second data bus for a data backup, and a control unit suitable for controlling the first data transferring/receiving unit and the second data transferring/receiving unit to be activated or inactivated according to whether a power failure occurs in the host.

Abstract translation: 一种存储单元，包括适于通过第一数据总线传送/接收数据以与主机通信的第一数据传送/接收单元，适于通过第二数据总线传送/接收数据以进行数据备份的第二数据传送/接收单元 以及适于根据主机中是否发生电源故障来控制要激活或失活的第一数据传送/接收单元和第二数据传送/接收单元的控制单元。

公开(公告)号：US20150127870A1

公开(公告)日：2015-05-07

申请号：US14106811

申请日：2013-12-15

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G06F13/28

CPC classification number: G11C7/1003 ,  G11C7/1048 ,  G11C7/18

Abstract: A semiconductor memory device includes a first global line suitable for inputting/outputting data from/to a first bank, a second global line suitable for inputting/outputting data from/to a second bank, a multi-purpose register (MPR) suitable for loading data having a predetermined value on the first global line in a training mode, a first data input/output (I/O) unit suitable for inputting/outputting data between one of the first and second global lines and a first data pad and selectively transferring data loaded on the first global line to the second global line in response to a bandwidth option in the training mode, and a second data I/O unit enabled in response to the bandwidth option, suitable for inputting/outputting data between the second global line and a second data pad.

Abstract translation: 半导体存储器件包括适于从第一组输入/输出数据的第一全局线，适于从第二组输入/输出数据的第二全局线，适于加载的多用途寄存器（MPR） 在训练模式下在第一全局线上具有预定值的数据，适于在第一和第二全局线之一之间输入/输出数据的第一数据输入/输出（I / O）单元和第一数据衬垫，并选择性地传送 响应于训练模式中的带宽选项而在第一全局线上加载到第二全局线的数据，以及响应于带宽选项使能的适于在第二全局线之间输入/输出数据的第二数据I / O单元 和第二数据垫。

公开(公告)号：US20150067201A1

公开(公告)日：2015-03-05

申请号：US14109511

申请日：2013-12-17

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F3/0658 ,  G06F3/0689 ,  G06F13/22 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor device includes a data storage suitable for storing a training data for a training operation, a data bus inversion (DBI) calculator suitable for calculating DBI information for the training data input from the data storage through global transmission lines, generating a DBI flag signal based on the DBI information and outputting a DBI data, which is the training data inverted according to the DBI flag signal, in response to a DBI signal, a first multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI data to a first channel in response to a training signal and the DBI signal and a second multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI flag signal to a second channel.

Abstract translation: 半导体器件包括适于存储用于训练操作的训练数据的数据存储器，适用于计算通过全局传输线从数据存储器输入的训练数据的DBI信息的数据总线反转（DBI）计算器，生成DBI标志信号 基于所述DBI信息，根据所述DBI信号输出作为根据所述DBI标志信号反转的训练数据的DBI数据，所述第一多路复用器适于选择性地输出通过所述全局传输从所述数据存储器输入的训练数据 行或DBI数据响应于训练信号和DBI信号发送到第一信道，以及第二多路复用器，适于选择性地将通过全局传输线或DBI标志信号从数据存储器输入的训练数据输出到第二信道。

公开(公告)号：US20150043293A1

公开(公告)日：2015-02-12

申请号：US14096801

申请日：2013-12-04

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG ,  Young-Do HUR ,  Tae-Woo KWON

IPC: G11C7/04

CPC classification number: G11C11/406 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/408

Abstract: A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer.

Abstract translation: 半导体存储器件包括多个存储体; 计数块，适用于对各个存储体的激活数进行计数，并选择激活数大于或等于给定数量的存储体; 以及适用于响应于刷新命令对存储体执行正常刷新操作并且对所选择的存储体执行附加刷新操作N次的刷新控制块，N是正整数。

公开(公告)号：US20140355371A1

公开(公告)日：2014-12-04

申请号：US14085531

申请日：2013-11-20

Applicant: SK hynix Inc.

Inventor： Chang-Hyun KIM ,  Choung-Ki SONG

IPC: G11C11/408

CPC classification number: G11C11/408 ,  G11C11/406

Abstract: An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at least a threshold number of times in each period that the active command is activated M (1≦M≦N) number of times, based on the N number of addresses stored in the address storage unit.

Abstract translation: 地址检测电路包括地址存储单元，适用于当激活命令时接收地址，并存储最近输入的N个地址; 以及地址确定单元，其适于确定当前输入到地址存储单元的地址是否已经在活动命令被激活的每个周期中至少输入了阈值次数M（1＆nlE; M＆nlE; N）次 在存储在地址存储单元中的N个地址上。

公开(公告)号：US20140355368A1

公开(公告)日：2014-12-04

申请号：US14098121

申请日：2013-12-05

Applicant: SK hynix Inc.

Inventor： Choung-Ki SONG

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C8/04 ,  G11C8/06 ,  G11C11/418 ,  G11C29/789

Abstract: An embodiment of the present invention provides a semiconductor, including a non-volatile storage unit suitable for storing one or more first addresses; an address storage unit suitable for storing the first addresses sequentially received from the non-volatile storage unit as second addresses while deleting previously stored second addresses identical to an input address of the first addresses, in a reset operation; and a cell array suitable for replacing one or more normal cells with one or more redundancy cells based on the second addresses in an access operation.

Abstract translation: 本发明的一个实施例提供了一种半导体，包括适于存储一个或多个第一地址的非易失性存储单元; 一种地址存储单元，用于在复位操作中将从非易失性存储单元顺序接收的第一地址存储为第二地址，同时删除与第一地址的输入地址相同的先前存储的第二地址; 以及适合于在访问操作中基于第二地址用一个或多个冗余单元替换一个或多个正常单元的单元阵列。

公开(公告)号：US20140006886A1

公开(公告)日：2014-01-02

申请号：US13844946

申请日：2013-03-16

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G11C29/14

CPC classification number: G11C29/14 ,  G11C29/46

Abstract: A memory includes a bank including a plurality of memory cells a command decoder configured to operate in synchronization with a clock signal and activate at least one of a plurality of commands including an active command, a write command, a calibration command, and an MRS command in response to a plurality of command signals, a test decoder configured to set the memory as a test mode in response to a plurality of address signals and the MRS command, and a test controller configured to activate at least one internal test command for test operating the bank at a time point that is decided based on counting information obtained by counting a test clock signal having a higher frequency than the clock signal, when the memory is set in the test mode.

Abstract translation: 存储器包括：包括多个存储器单元的存储器，命令解码器，被配置为与时钟信号同步地操作，并激活多个命令中的至少一个，包括有效命令，写命令，校准命令和MRS命令 响应于多个命令信号，测试解码器被配置为响应于多个地址信号和MRS命令将存储器设置为测试模式，以及测试控制器，被配置为激活至少一个内部测试命令用于测试操作 当存储器被设置在测试模式时，在基于通过对具有比时钟信号更高的频率的测试时钟信号进行计数而获得的计数信息来确定的时间点的存储体。

公开(公告)号：US20140003183A1

公开(公告)日：2014-01-02

申请号：US13716806

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Choung-Ki SONG

IPC: G11C8/06

CPC classification number: G11C8/06

Abstract: A memory device includes a plurality of banks, a plurality of address buffers configured to receive addresses, and a buffer control unit configured to deactivate one or more of the plurality of address buffers when the number of activated banks among the plurality of banks is a prescribed number.

Abstract translation: 存储器装置包括多个存储体，多个地址缓冲器，被配置为接收地址;以及缓冲器控制单元，配置为当多个存储体中的激活的存储体的数目是规定的时间时，停止多个地址缓冲器中的一个或多个 数。