公开(公告)号：US10250133B2

公开(公告)日：2019-04-02

申请号：US15652447

申请日：2017-07-18

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  H03K3/356

Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.

公开(公告)号：US12087368B2

公开(公告)日：2024-09-10

申请号：US17548096

申请日：2021-12-10

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Arpit Vijayvergia ,  Vikas Rana

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C16/0458 ,  G11C16/24

Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.

公开(公告)号：US11881280B2

公开(公告)日：2024-01-23

申请号：US17534136

申请日：2021-11-23

Applicant: STMicroelectronics International N.V.

Inventor： Shivam Kalla ,  Vikas Rana

IPC: G05F3/02 ,  G05F1/10 ,  G11C5/14 ,  G11C11/56 ,  H02M1/00 ,  H03K5/24 ,  G05F3/26 ,  H02M3/07 ,  G11C16/30

CPC classification number: G11C5/145 ,  G05F3/262 ,  G11C5/147 ,  G11C11/5635 ,  G11C16/30 ,  H02M1/0003 ,  H02M3/07 ,  H03K5/24

Abstract: An integrated circuit includes a non-volatile memory, a charge pump that generates high voltages for programming operations of the non-volatile memory array, and a charge pump regulator that controls a slew rate of the charge pump. The charge pump regulator generates a sense current indicative of the slew rate and adjusts a frequency of a clock signal provided to the charge pump based on the sense current.

公开(公告)号：US11183924B2

公开(公告)日：2021-11-23

申请号：US17021013

申请日：2020-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/07 ,  H03K19/096 ,  G05F1/10

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

公开(公告)号：US10050524B1

公开(公告)日：2018-08-14

申请号：US15800896

申请日：2017-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: H02M3/18 ,  H02M3/07 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02

Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

公开(公告)号：US09129685B2

公开(公告)日：2015-09-08

申请号：US14266468

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: G11C11/4193 ,  G11C11/4195 ,  G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US11935607B2

公开(公告)日：2024-03-19

申请号：US17837377

申请日：2022-06-10

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Vivek Tyagi

IPC: G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G11C29/52

CPC classification number: G11C29/12005 ,  G11C29/18 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

公开(公告)号：US11908528B2

公开(公告)日：2024-02-20

申请号：US17527031

申请日：2021-11-15

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas Rana ,  Arpit Vijayvergia

IPC: G11C16/30 ,  H02M3/07 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C5/145 ,  H02M3/077

Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.

公开(公告)号：US11563373B2

公开(公告)日：2023-01-24

申请号：US17494451

申请日：2021-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Neha Dalal

IPC: H02M3/07 ,  G11C5/14

Abstract: A charge pump circuit includes a first charge pump stage circuit coupled in series with a second charge pump stage circuit. A discharge circuit operates to discharge the charge pump circuit. The discharge circuit includes: a first switched circuit coupled to a first output of the first charge pump stage circuit and configured, when actuated, to discharge the first output; and a second switched circuit coupled to a second output of the second charge pump stage circuit and configured, when actuated, to discharge the second output. A discharge control circuit actuates the first switched discharge circuit to discharge the first output and then, after the first output is fully discharged, actuates the second switched discharge circuit to discharge the second output.

公开(公告)号：US11551731B2

公开(公告)日：2023-01-10

申请号：US17321344

申请日：2021-05-14

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Arpit Vijayvergia

IPC: G11C7/00 ,  G11C7/06 ,  H03K19/20

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.