公开(公告)号：US20170278892A1

公开(公告)日：2017-09-28

申请号：US15230055

申请日：2016-08-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14689

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

公开(公告)号：US09419039B2

公开(公告)日：2016-08-16

申请号：US14644795

申请日：2015-03-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nayera Ahmed ,  Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

Abstract translation: 在第二导电类型的掺杂半导体衬底上延伸的第一导电类型的掺杂半导体层中形成的光电二极管之间的绝缘结构，所述绝缘结构包括与半导体层交叉的沟槽，所述沟壁涂覆有绝缘层， 该沟槽被一个导电材料填充并且被比该半导体层更重掺杂的P掺杂区包围。

公开(公告)号：US12075178B2

公开(公告)日：2024-08-27

申请号：US17986505

申请日：2022-11-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Thomas Dalleau

IPC: H04N25/77 ,  H04N25/75

CPC classification number: H04N25/77 ,  H04N25/75

Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.

公开(公告)号：US10910428B2

公开(公告)日：2021-02-02

申请号：US16212790

申请日：2018-12-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Sonarith Chhun

IPC: H01L27/146

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US10566376B2

公开(公告)日：2020-02-18

申请号：US16112241

申请日：2018-08-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Frédéric Lalanne ,  Pierre Emmanuel Marie Malinge

IPC: H01L27/146 ,  H04N5/378

Abstract: An image sensor device may include an array of image sensing pixels arranged in rows and columns. Each image sensing pixel may include an image sensing photodiode, a first source follower transistor coupled to the image sensing photodiode, and a switch coupled to the image sensing photodiode. Each image sensor device may include a second source follower transistor coupled to the switch, and a row selection transistor coupled to the first and second source follower transistors.

公开(公告)号：US10535693B2

公开(公告)日：2020-01-14

申请号：US15916912

申请日：2018-03-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode.

公开(公告)号：US10531022B2

公开(公告)日：2020-01-07

申请号：US15995249

申请日：2018-06-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H04N5/353 ,  H01L27/146 ,  H04N5/372 ,  H04N5/378 ,  H04N5/363

Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

公开(公告)号：US10475848B2

公开(公告)日：2019-11-12

申请号：US15839011

申请日：2017-12-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/148 ,  H01L27/146 ,  H04N9/00

Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.

公开(公告)号：US20190086519A1

公开(公告)日：2019-03-21

申请号：US16194985

申请日：2018-11-19

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Boris Rodrigues Goncalves ,  Marie Guillon ,  Yvon Cazaux ,  Benoit Giffard

IPC: G01S7/486 ,  H01L27/146 ,  G01S7/491 ,  H04N5/374

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

公开(公告)号：US20180012926A1

公开(公告)日：2018-01-11

申请号：US15703246

申请日：2017-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14638 ,  H01L27/14689

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.