公开(公告)号：US20160170521A1

公开(公告)日：2016-06-16

申请号：US14712953

申请日：2015-05-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Shin Il CHOI ,  Jae Neung KIM ,  Su Bin BAE ,  Yu-Gwang JEONG

IPC: G06F3/044 ,  C23F1/00 ,  G06F1/16

CPC classification number: G06F3/044 ,  G06F2203/04103 ,  G06F2203/04111 ,  G06F2203/04112

Abstract: A transparent electrode pattern includes a first electrode including a first lower conductive layer and a first upper conductive layer located on the first lower conductive layer and a second electrode spaced apart from the first electrode and including a second lower conductive layer and a second upper conductive layer positioned on the second lower conductive layer. The first and second lower conductive layers may include a metal nanowire. The first and second upper conductive layers may include a transparent conductive material that is dry-etchable.

Abstract translation: 透明电极图案包括第一电极，其包括第一下导电层和位于第一下导电层上的第一上导电层和与第一电极间隔开的第二电极，并且包括第二下导电层和第二上导电层 位于第二下导电层上。 第一和第二下导电层可以包括金属纳米线。 第一和第二上导电层可以包括可干蚀刻的透明导电材料。

公开(公告)号：US20150357356A1

公开(公告)日：2015-12-10

申请号：US14621303

申请日：2015-02-12

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Neung KIM ,  Yu-Gwang JEONG ,  Su-Bin BAE ,  Yun-Jong YEO

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78669 ,  H01L29/7869

Abstract: A thin film transistor array substrate and a method of manufacturing the thin film transistor array substrate are provided. The thin film transistor array substrate includes: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; a semiconductor pattern disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor pattern and spaced apart from each other; and a hard mask pattern disposed on the source electrode and the drain electrode.

Abstract translation: 提供薄膜晶体管阵列基板和制造薄膜晶体管阵列基板的方法。 薄膜晶体管阵列基板包括：基板; 设置在所述基板上的栅电极; 设置在栅电极上的栅极绝缘层; 设置在所述栅绝缘层上的半导体图案; 源电极和漏电极，设置在半导体图案上并彼此间隔开; 以及设置在源电极和漏电极上的硬掩模图案。

公开(公告)号：US20150194534A1

公开(公告)日：2015-07-09

申请号：US14666461

申请日：2015-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su LEE ,  Yoon Ho KHANG ,  Dong Jo KIM ,  Hyun Jae NA ,  Sang Ho PARK ,  Se Hwan YU ,  Chong Sup CHANG ,  Dae Ho KIM ,  Jae Neung KIM ,  Myoung Geun CHA ,  Sang Gab KIM ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US20150108489A1

公开(公告)日：2015-04-23

申请号：US14579542

申请日：2014-12-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Joo-Han KIM ,  Ki-Yong SONG ,  Dong-Ju YANG ,  Hee-Joon KIM ,  Yeo-Geon YOON ,  Sung-Hen CHO ,  Chang-Hoon KIM ,  Jae-Hong KIM ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Ji-Young PARK

IPC: H01L23/00 ,  H01L27/12

CPC classification number: H01L24/05 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L2224/04042 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/00

Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Abstract translation: 公开了布线的接触部分及其制造方法。 根据实施例的布线的接触部分包括：基板; 设置在所述基板上的导电层; 设置在所述导电层上并具有接触孔的层间绝缘层; 设置在所述导电层上并填充所述接触孔的金属层; 以及透明电极，设置在所述层间绝缘层上并连接到所述金属层，其中所述层间绝缘层包括下绝缘层和设置在所述下绝缘层上的上绝缘层，所述下绝缘层在所述接触孔处被底切， 并且金属层填充在下绝缘层被切下的部分。

公开(公告)号：US20150097179A1

公开(公告)日：2015-04-09

申请号：US14262761

申请日：2014-04-27

Applicant: Samsung Display Co., LTD.

Inventor： Dae-Ho KIM ,  Hyun-Jae NA ,  Jae-Neung KIM ,  Yu-Gwang JEONG ,  Myoung-Geun CHA ,  Sang-Gab KIM

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/41733

Abstract: A display substrate includes an active pattern, a gate electrode, a first insulation layer and a pixel electrode. The active pattern is disposed on a base substrate. The active pattern includes a metal oxide semiconductor. The gate electrode overlaps the active pattern. The first insulation layer covers the gate electrode and the active pattern, and a contact hole is defined in the first insulation layer. The pixel electrode is electrically connected to the active pattern via the contact hole penetrating the first insulation layer. A first angle defined by a bottom surface of the first insulation layer and a sidewall of the first insulation layer exposed by the contact hole is between about 30° and about 50°.

Abstract translation: 显示基板包括有源图案，栅电极，第一绝缘层和像素电极。 有源图案设置在基底基板上。 有源图案包括金属氧化物半导体。 栅电极与有源图案重叠。 第一绝缘层覆盖栅电极和有源图案，并且在第一绝缘层中限定接触孔。 像素电极经由穿过第一绝缘层的接触孔电连接到有源图案。 由第一绝缘层的底表面和由接触孔露出的第一绝缘层的侧壁限定的第一角度在约30°至约50°之间。