公开(公告)号：US20250016980A1

公开(公告)日：2025-01-09

申请号：US18629799

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Bongsoo Kim ,  Yongkwan Kim ,  Jongmin Kim ,  Taejin Park ,  Chansic Yoon ,  Jinwoo Han

IPC: H10B12/00

Abstract: A semiconductor device includes an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction and crossing central portions of the active patterns; a bit line structure contacting first portions of the active patterns adjacent to a first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction oblique with respect to the first direction. The active patterns arranged side by side in the second direction form an active column.

公开(公告)号：US12166132B2

公开(公告)日：2024-12-10

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Mintae Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Hyunmog Park ,  Kiseok Lee

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20240315006A1

公开(公告)日：2024-09-19

申请号：US18424447

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Junhyeok Ahn ,  Chansic Yoon ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate, a first contact structure on a central portion of each active pattern, a bit line structure on the first contact structure, a second contact structure on an end portion of each active pattern, a third contact structure on the second contact structure, a filling pattern between the bit line structure and the third contact structure and including a void, and a capacitor electrically connected to the third contact structure. The active pattern array includes active pattern rows spaced apart from each other in a first direction, and each active pattern row includes the active patterns spaced apart from each other in a second direction. Each active pattern extends in a third direction, and the active patterns in each active pattern row are aligned in the second direction.

公开(公告)号：US20240292601A1

公开(公告)日：2024-08-29

申请号：US18460522

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HONGJUN LEE ,  Keunnam Kim ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/485

Abstract: A semiconductor device includes a substrate including an active region, a word line and a bit line that overlap the active region while crossing the active region, a bit line capping layer that is disposed on the bit line, a direct contact that connects the active region and the bit line, and a buried contact that is connected to the active region. Opposite sides of the bit line capping layer have asymmetric shapes.

公开(公告)号：US12052855B2

公开(公告)日：2024-07-30

申请号：US18165692

申请日：2023-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/30 ,  G11C5/063

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US20240074155A1

公开(公告)日：2024-02-29

申请号：US18236143

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyuk Kim ,  Taegyu Kang ,  Seokho Shin ,  Kiseok Lee ,  Sangho Lee ,  Keunnam Kim ,  Seokhan Park ,  Joongchan Shin ,  Moonyoung Jeong ,  Eunju Cho

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first direction, first and second active patterns on the bit line, a back-gate electrode between the first and second active patterns and extending across the bit line and in a second direction that is perpendicular to the first direction, a first word line extending in the second direction at one side of the first active pattern, a second word line extending in the second direction at the other side of the second active pattern, and a contact pattern connected to each of the first and second active patterns, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer.

公开(公告)号：US20230413525A1

公开(公告)日：2023-12-21

申请号：US18189391

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeran Lee ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H01L28/90 ,  H10B12/50 ,  H10B12/488

Abstract: A semiconductor memory includes a substrate having a plurality of active regions, a plurality of word lines formed in the substrate and disposed in a plurality of word line trenches extending in a first direction, a plurality of cell pad patterns on the plurality of active regions, a plurality of bit line structures formed on the substrate and extending in a second direction perpendicular to the first direction, and a plurality of isolation insulating patterns filling at least a portion of a plurality of isolation trenches extending between the plurality of cell pad patterns in the second direction, wherein each of the plurality of isolation insulating patterns includes an isolation insulating line portion and an isolation insulating spacer portion connected to each other and forming an integral body. The isolation insulating line portion and the isolation insulating spacer portion being disposed in alternating ones of the plurality of isolation trenches and extend in the second direction.

公开(公告)号：US11770926B2

公开(公告)日：2023-09-26

申请号：US17530818

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok Ahn ,  Kiseok Lee ,  Huijung Kim

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

公开(公告)号：US11751378B2

公开(公告)日：2023-09-05

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Kiseok Lee ,  Seungjae Jung ,  Joongchan Shin ,  Taehyun An ,  Moonyoung Jeong ,  Sangyeon Han

IPC: H10B12/00 ,  H01L29/08

CPC classification number: H10B12/30 ,  H01L29/0847 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US20230189501A1

公开(公告)日：2023-06-15

申请号：US18165692

申请日：2023-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung KIM ,  Taehyun An ,  Kiseok Lee ,  Yoosang Hwang

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/30 ,  G11C5/063

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.