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公开(公告)号：US20210117402A1
公开(公告)日：2021-04-22
申请号：US17028542
申请日：2020-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyonsok LEE , Mirae Jeong , Jiyoung Kang , Kyunghwan Lee , Jeonghyeon Lee , Junhyuk Lee
IPC: G06F16/23 , G06F16/901
Abstract: A method of updating a server knowledge graph, is performed by a server and includes obtaining a server knowledge graph of the server, and obtaining a plurality of device knowledge graphs by receiving a device knowledge graph from each of a plurality of devices. The method further includes generating a knowledge graph for server knowledge graph extension, based on the obtained plurality of device knowledge graphs, and updating the obtained server knowledge graph, using the generated knowledge graph for server knowledge graph extension.
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公开(公告)号：US10971238B2
公开(公告)日：2021-04-06
申请号：US16714941
申请日：2019-12-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kohji Kanamori , Yongseok Kim , Kyunghwan Lee , Junhee Lim
IPC: G11C16/34 , G11C16/04 , H01L27/11582 , H01L27/11565 , H01L27/11573 , G11C16/14 , G11C16/10 , G11C16/26
Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided.
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公开(公告)号：US12193343B2
公开(公告)日：2025-01-07
申请号：US17192093
申请日：2021-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol Kim , Yongseok Kim , Hyeoungwon Seo , Sungwon Yoo , Kyunghwan Lee , Jaeho Hong
IPC: H10N70/00 , H01L29/423 , H10B63/00
Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.
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公开(公告)号：US12191136B2
公开(公告)日：2025-01-07
申请号：US18098174
申请日：2023-01-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol Kim , Yongseok Kim , Huijung Kim , Satoru Yamada , Sungwon Yoo , Kyunghwan Lee , Jaeho Hong
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号：US12095876B2
公开(公告)日：2024-09-17
申请号：US18300066
申请日：2023-04-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jungho Park , Yul Kim , Sejeong Kwon , Soohyung Kim , Wonsuk Yang , Kyunghwan Lee , Junhyuk Lee
CPC classification number: H04L67/535 , G06F16/35 , H04L41/16 , H04L43/04 , H04L67/02
Abstract: An electronic apparatus is provided. The electronic apparatus includes a communication interface, a memory storing log data with respect to external devices connected to the electronic apparatus, and a processor configured to identify a plurality of external devices having a history of being connected to the same internet protocol (IP) based on the log data, acquire, based on the log data, a first feature vector with respect to a relationship between the plurality of external devices and a second feature vector with respect to each of the plurality of external devices, acquire a graph of the relationship between the plurality of external devices based on the first feature vector and the second feature vector, and define at least one group configured by the plurality of external devices based on the graph.
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Patent Agency Ranking
公开(公告)号：US20240276713A1
公开(公告)日：2024-08-15
申请号：US18537987
申请日：2023-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonil Lee , Kyunghwan Lee , Juho Lee
IPC: H10B12/00 , H01L29/423 , H01L29/788
CPC classification number: H10B12/485 , H01L29/42324 , H01L29/7889 , H10B12/315 , H10B12/482 , H10B12/488
Abstract: A semiconductor memory device includes a memory cell that extends in a first horizontal direction, a second horizontal direction that intersects the first horizontal direction, and a vertical direction. The memory cell includes a first transistor including a first channel structure, a second transistor including a second channel structure, a charge storage element electrically connected to a first end of the second channel structure and adjacent to the first channel structure a first bit line electrically connected to a first end of the first channel structure and that extends in the second horizontal direction, a selection line electrically connected to a second end of the first channel structure and that extends in the second horizontal direction, a second bit line electrically connected to a second end of the second channel structure and that extends in the second horizontal direction, and a gate line that extends in the vertical direction.
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公开(公告)号：US20240224494A1
公开(公告)日：2024-07-04
申请号：US18414893
申请日：2024-01-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan Lee , Yongseok Kim , Ilgweon Kim , Huijung Kim , Sungwon Yoo , Minhee Cho
IPC: H10B12/00
CPC classification number: H10B12/00
Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.
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公开(公告)号：US11943925B2
公开(公告)日：2024-03-26
申请号：US17335763
申请日：2021-06-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Jaeho Hong , Yongseok Kim , Ilgweon Kim , Hyeoungwon Seo , Sungwon Yoo , Kyunghwan Lee
IPC: G11C8/14 , G11C7/18 , H01L25/065 , H10B43/10 , H10B43/27
CPC classification number: H10B43/27 , G11C7/18 , G11C8/14 , H01L25/065 , H10B43/10
Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.
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公开(公告)号：US20240099015A1
公开(公告)日：2024-03-21
申请号：US18368067
申请日：2023-09-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonil LEE , Kyunghwan Lee
IPC: H10B51/20
Abstract: A semiconductor device includes a substrate. A plurality of horizontal structures is stacked on the substrate and spaced apart from each other. A plurality of vertical structures penetrates through the plurality of horizontal structures. Each of the plurality of vertical structures includes a vertical source line, a vertical bit line, a channel layer, and a dielectric layer. The channel layer is in direct contact with the vertical source line and the vertical bit line. The dielectric layer is disposed between the plurality of horizontal structures and the channel layer. Each of the plurality of horizontal structures includes a first conductive layer, a ferroelectric layer surrounding at least a portion of the first conductive layer, and a second conductive layer disposed between the ferroelectric layer and the dielectric layer.
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公开(公告)号：US11917805B2
公开(公告)日：2024-02-27
申请号：US17541584
申请日：2021-12-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan Lee , Yongseok Kim , Ilgweon Kim , Huijung Kim , Sungwon Yoo , Minhee Cho
IPC: H10B12/00
CPC classification number: H10B12/00
Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.
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