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41.发明授权System and method for implementing an integrated circuit having dynamically variable power limit 有权用于实现具有动态可变功率限制的集成电路的系统和方法公开(公告)号：US08086884B2
公开(公告)日：2011-12-27
申请号：US10320586
申请日：2002-12-16
申请人： Samuel Naffziger
发明人： Samuel Naffziger
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit having a dynamically variable power limit is provided. The integrated circuit comprises power management logic operable to receive notification of a dynamically set power limit value and operable to dynamically regulate the integrated circuit's power consumption to comply with the dynamically set power limit value.
摘要翻译： 提供具有动态可变功率限制的集成电路。 集成电路包括电源管理逻辑，其可操作以接收动态设置的功率限制值的通知，并可操作以动态地调节集成电路的功率消耗以符合动态设置的功率限制值。
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公开(公告)号：US20110261064A1
公开(公告)日：2011-10-27
申请号：US12766403
申请日：2010-04-23
CPC分类号： G11C11/412 , G11C11/413 , G11C15/00
摘要： A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value.
摘要翻译： 提供了一种方法，装置，计算机芯片，电路板，计算机和系统，其中数据存储在低电压，可屏蔽的存储器中。 还提供了一种用数据编码的计算机可读存储设备，用于使制造设备适配以创建设备。 如果与存储器单元相关联的第一访问参数与第一预定值相匹配，并且如果与存储单元相关联的第二访问参数与第二预定值匹配，则该方法包括将存储单元中的数据值存储在存储设备中 。 如果第一访问参数不同于第一预定值，则该方法还包括在存储设备中的存储单元中维护数据值。 该装置包括分别可操作地耦合在一起并与第一和第二访问参数相关联的第一和第二对访问参数端口。 如果第一访问参数与第一预定值相匹配，则第一和第二对访问参数端口可以被适配为允许通过第一和第二对访问参数端口访问，并且如果第二访问参数与第二预定值 值。
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公开(公告)号：US07558317B2
公开(公告)日：2009-07-07
申请号：US11118740
申请日：2005-04-29
IPC分类号： H04B3/46
CPC分类号： G06F1/12
摘要： Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.
摘要翻译： 公开了用于时钟域之间的同步数据传输的边缘校准的系统和方法。 示例性方法可以包括：至少部分地基于用于时钟域之间的同步数据传输的选择时钟信号来比较驱动时钟信号与接收时钟信号，产生选择时钟信号，以及配置数据路径，使得数据到达 早期时钟域在所需的逻辑时钟周期。
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44.发明授权公开(公告)号：US07477712B2
公开(公告)日：2009-01-13
申请号：US11118632
申请日：2005-04-29
IPC分类号： H04L7/02
摘要： Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.
摘要翻译： 公开了在时钟域之间实现同步数据传输的系统和方法。 示例性系统可以包括适应性数据路径，其具有用于从第一时钟域接收信号的输入和第二时钟域中的输出。 控制器可操作地与适应性数据路径相关联。 控制器响应于操作参数来配置适应性数据路径，以便基于第一和第二时钟之间的测量延迟，将从第一时钟域接收的信号上的逻辑时钟脉冲与第二时钟域中的相同逻辑时钟脉冲对准 域名
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45.发明授权公开(公告)号：US07401245B2
公开(公告)日：2008-07-15
申请号：US11118600
申请日：2005-04-29
CPC分类号： G06F1/12
摘要： Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.
摘要翻译： 公开了用于实现时钟域之间的同步数据传输的计数校准的系统和方法。 示例性系统可以包括用于确定早期时钟域和后期时钟域之间的等待时间的计数校准电路。 系统还可以包括至少部分地基于等待时间来配置用于时钟域之间的同步数据传输的数据路径。
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公开(公告)号：US20070022273A1
公开(公告)日：2007-01-25
申请号：US11184318
申请日：2005-07-19
申请人： Samuel Naffziger , Don Soltis
发明人： Samuel Naffziger , Don Soltis
IPC分类号： G06F9/40
CPC分类号： G06F9/3861 , G06F9/3012 , G06F9/3826 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： Systems and methods for error recovery in an integer execution unit of a multi-core processor are disclosed. In an exemplary embodiment a method may comprise checking parity for a transaction in an execution data path having parallel data registers. The method may also comprise copying one of the parallel data registers to a corrupt data register if parity fails.
摘要翻译： 公开了一种用于多核处理器的整数执行单元中的错误恢复的系统和方法。 在示例性实施例中，方法可以包括检查具有并行数据寄存器的执行数据路径中的事务的奇偶校验。 如果奇偶校验失败，该方法还可以包括将并行数据寄存器中的一个复制到损坏的数据寄存器。
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47.发明申请公开(公告)号：US20060245529A1
公开(公告)日：2006-11-02
申请号：US11118632
申请日：2005-04-29
IPC分类号： H04L7/02
摘要： Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains
摘要翻译： 公开了在时钟域之间实现同步数据传输的系统和方法。 示例性系统可以包括适应性数据路径，其具有用于从第一时钟域接收信号的输入和第二时钟域中的输出。 控制器可操作地与适应性数据路径相关联。 控制器响应于操作参数来配置适应性数据路径，以便基于第一和第二时钟之间的测量延迟，将从第一时钟域接收的信号上的逻辑时钟脉冲与第二时钟域中的相同逻辑时钟脉冲对准 域名
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公开(公告)号：US20060244642A1
公开(公告)日：2006-11-02
申请号：US11118740
申请日：2005-04-29
IPC分类号： H03M1/10
CPC分类号： G06F1/12
摘要： Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.
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公开(公告)号：US07047437B2
公开(公告)日：2006-05-16
申请号：US10021170
申请日：2001-12-12
IPC分类号： G06F11/00
CPC分类号： H04L1/1642
摘要： A system and a method of providing error detection and correction of transmission of multiple flits between sending and receiving agents connected together in a network or computer interconnect environment is disclosed that comprises embedding a sequence identifier in each flit prior to transmission, sending each flit to a connected receiving agent, examining the sequence identifiers of each flit being received and requesting the sending agent to resend a flit if the sequence identifier for that flit is determined to be incorrect.In a preferred embodiment of the present invention, the sequence identifier is embedded in the control portion of the flit and comprises a sequence number that is incremented or otherwise changed in a predictable manner, so that the order of flits being received is predicted. If the sequence number for a flit is different that expected, the receiving agent requests that it be resent.
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公开(公告)号：US20050246114A1
公开(公告)日：2005-11-03
申请号：US10835506
申请日：2004-04-29
申请人： Randy Rannow , Samuel Naffziger , Karl Bois , Bradley Winick
发明人： Randy Rannow , Samuel Naffziger , Karl Bois , Bradley Winick
CPC分类号： G01R15/20
摘要： Methodology, systems, and media associated with sensing a magnetic field produced by an electrical signal flowing through a conductor are described. One exemplary system may include a connector that conveys the electrical signal between conductors and an in-line field sensor positioned and configured to sense the magnetic field produced by the electrical signal without affecting the electrical signal.
摘要翻译： 描述了与感测由流过导体的电信号产生的磁场相关联的方法，系统和介质。 一个示例性系统可以包括传送导体之间的电信号的连接器和定位和配置为感测由电信号产生的磁场而不影响电信号的在线现场传感器。
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