公开(公告)号：US11335790B2

公开(公告)日：2022-05-17

申请号：US16577176

申请日：2019-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H01L29/51 ,  H01L27/11514 ,  H01L21/28 ,  H01L29/417

Abstract: A semiconductor structure contains a semiconductor channel extending between a source region and a drain region, at least one gate electrode, a ferroelectric material portion located between the semiconductor channel and the at least one gate electrode, a front-side gate dielectric located between the ferroelectric material portion and the semiconductor channel, and a backside gate dielectric located between the ferroelectric material portion and the at least one gate electrode. The front-side gate dielectric and the backside gate dielectric have a dielectric constant greater than 7.9 and a band gap greater than a band gap of the ferroelectric material portion.

公开(公告)号：US11302713B2

公开(公告)日：2022-04-12

申请号：US16912279

申请日：2020-06-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Kumar Baraskar ,  Raghuveer S. Makala ,  Peter Rabkin

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L21/02 ,  H01L21/311 ,  H01L21/78 ,  H01L29/66 ,  H01L25/00 ,  H01L23/00 ,  H01L29/20

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

公开(公告)号：US11239204B2

公开(公告)日：2022-02-01

申请号：US16694400

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Yangyin Chen ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.

公开(公告)号：US11164883B2

公开(公告)日：2021-11-02

申请号：US16019904

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani ,  Jayavel Pachamuthu

IPC: H01L27/11582 ,  G11C8/14 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US11074976B2

公开(公告)日：2021-07-27

申请号：US16551553

申请日：2019-08-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  G11C16/14 ,  G11C16/30 ,  H03H11/28 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: A memory system is provided with technology for performing temperature dependent impedance mitigation, in addition to or instead of other techniques to compensate for differences in impedance. For example, the memory system comprises a plurality of non-volatile memory cells, a first pathway connected to the plurality of non-volatile memory cells, a second pathway connected to the plurality of non-volatile memory cells, and a control circuit connected to the first pathway and the second pathway. The control circuit is configured to compensate based on temperature for a temperature dependent impedance mismatch between the first pathway and the second pathway during a memory operation on the plurality of non-volatile memory cells.

公开(公告)号：US10991721B2

公开(公告)日：2021-04-27

申请号：US16886081

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Raghuveer S. Makala ,  Masaaki Higashitani

IPC: H01L29/76 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L27/11524 ,  H01L21/28

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.

公开(公告)号：US10978145B2

公开(公告)日：2021-04-13

申请号：US16540862

申请日：2019-08-14

Applicant: SanDisk Technologies LLC

Inventor： Biswajit Ray ,  Peter Rabkin ,  Mohan Dunga ,  Gerrit Jan Hemink ,  Changyuan Chen

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/407 ,  G11C11/406 ,  G11C11/4074

Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

公开(公告)号：US10923196B1

公开(公告)日：2021-02-16

申请号：US16781589

申请日：2020-02-04

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  H01L27/06 ,  G11C16/34

Abstract: An apparatus for erasing non-volatile storage elements in a non-volatile memory system is disclosed. The apparatus has consistent speed in gate induced drain leakage (GIDL) erase across the operating temperature of the memory system. In one aspect, a voltage source outputs an erase voltage to NAND strings. The NAND strings may draw a GIDL erase current in response to the erase voltage. The amount of GIDL erase current for a given erase voltage is highly temperature dependent. The GIDL erase current may be sampled, and the erase voltage regulated based on the GIDL erase current. Therefore, the GIDL erase current, as well as erase speed, may be kept uniform across operating temperatures.

公开(公告)号：US10763271B2

公开(公告)日：2020-09-01

申请号：US16019961

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani ,  Jayavel Pachamuthu

IPC: H01L27/11 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.

公开(公告)号：US10650898B1

公开(公告)日：2020-05-12

申请号：US16182031

申请日：2018-11-06

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Kwang-Ho Kim ,  Masaaki Higashitani ,  Yingda Dong

IPC: G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11524

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.