公开(公告)号：US09859300B2

公开(公告)日：2018-01-02

申请号：US14700652

申请日：2015-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daiki Nakamura ,  Hisao Ikeda ,  Kouhei Toyotaka

IPC: H01L27/12 ,  H01L27/32 ,  H01L51/52

CPC classification number: H01L27/12 ,  H01L27/1255 ,  H01L27/322 ,  H01L27/323 ,  H01L27/3246 ,  H01L27/3251 ,  H01L27/3262 ,  H01L27/3279 ,  H01L51/5218 ,  H01L51/5228 ,  H01L51/5234 ,  H01L51/524 ,  H01L51/5284 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/5315 ,  H01L2251/5338

Abstract: To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element. The resistance of the second conductive layer is lower than that of the second electrode.

公开(公告)号：US09735285B2

公开(公告)日：2017-08-15

申请号：US15296432

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Kosei Noda ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Hikaru Harada

IPC: H01L29/04 ,  H01L29/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/108 ,  H01L27/11 ,  H01L27/12 ,  H01L49/02 ,  G06F15/76 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7869 ,  G06F15/76 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78696

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

公开(公告)号：US09666678B2

公开(公告)日：2017-05-30

申请号：US13799246

申请日：2013-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kei Takahashi ,  Kouhei Toyotaka ,  Masashi Tsubuku ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L29/26 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/26 ,  G06K19/07758 ,  G11C7/00 ,  G11C19/28 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US09494830B2

公开(公告)日：2016-11-15

申请号：US14290263

申请日：2014-05-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroyuki Miyake ,  Kouhei Toyotaka ,  Masahiko Hayakawa ,  Daisuke Matsubayashi ,  Shinpei Matsuda

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/1343 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The following semiconductor device provides high reliability and a narrower frame width. The semiconductor device includes a driver circuit and a pixel portion. The driver circuit has a first transistor including a first gate and a second gate electrically connected to each other with a semiconductor film sandwiched therebetween, and a second transistor electrically connected to the first transistor. The pixel portion includes a third transistor, a liquid crystal element, and a capacitor. The liquid crystal element includes a first transparent conductive film electrically connected to the third transistor, a second conductive film, and a liquid crystal layer. The capacitor includes the first conductive film, a third transparent conductive film, and a nitride insulating film. The nitride insulating film is positioned between the first transparent conductive film and the third transparent conductive film, and positioned between the semiconductor film and the second gate of the first transistor.

Abstract translation: 以下半导体器件提供高可靠性和较窄的帧宽度。 半导体器件包括驱动电路和像素部分。 驱动电路具有包括第一栅极和第二栅极的第一晶体管，其中夹在其间的半导体膜彼此电连接，第二晶体管与第一晶体管电连接。 像素部分包括第三晶体管，液晶元件和电容器。 液晶元件包括与第三晶体管电连接的第一透明导电膜，第二导电膜和液晶层。 电容器包括第一导电膜，第三透明导电膜和氮化物绝缘膜。 氮化物绝缘膜位于第一透明导电膜和第三透明导电膜之间，位于第一晶体管的半导体膜和第二栅极之间。

公开(公告)号：US09424950B2

公开(公告)日：2016-08-23

申请号：US14315601

申请日：2014-06-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kouhei Toyotaka ,  Jun Koyama ,  Hiroyuki Miyake

IPC: G11C19/00 ,  G11C19/28 ,  G09G3/32 ,  G09G3/36

CPC classification number: H01L27/124 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0626 ,  G09G2330/021 ,  G11C19/28 ,  G11C19/287 ,  H01L27/1225 ,  H01L29/7869

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

Abstract translation: 半导体器件包括具有相同导电类型的第一和第二晶体管和电路。 第一晶体管的源极和漏极之一与第二晶体管的源极和漏极电连接。 第一和第三电位通过各自的布线提供给电路。 第二电位和第一时钟信号分别被提供给第一和第二晶体管的源极和漏极中的其它电极。 第二个时钟信号被提供给电路。 第三电位高于高于第一电位的第二电位。 第四个电位等于或高于第三个电位。 第一时钟信号交替第二和第四电位，第二时钟信号交替第一和第三电位。 该电路控制第一和第二晶体管的栅极与布线之间的电连接。

公开(公告)号：US09208742B2

公开(公告)日：2015-12-08

申请号：US14325603

申请日：2014-07-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki Miyake ,  Kouhei Toyotaka ,  Shunpei Yamazaki

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/0291 ,  G11C19/28 ,  H01L27/1222 ,  H01L27/124

Abstract: To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n−3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.

Abstract translation: 提供一种包括通过设计栅极驱动器电路而获得的窄边框的半导体器件。 显示装置的栅极驱动器包括移位寄存器单元，解复用器电路和n个信号线。 通过将用于发送时钟信号的n条信号线连接到移位寄存器单元的一级，可以输出（n-3）个输出信号。 较大的n变得越小，用于传输不有助于输出的时钟信号的信号线的速率越小; 因此，与移动寄存器单元的一个级输出一个输出信号的常规结构相比，移位寄存器单元部分的面积较小。 因此，栅极驱动器电路可以具有窄的边框。

公开(公告)号：US09111483B2

公开(公告)日：2015-08-18

申请号：US13718402

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroyuki Miyake ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Toru Tanabe ,  Makoto Kaneyasu ,  Masashi Fujita

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2370/08

Abstract: To provide a display device with high image quality and fewer terminals. The present invention is made with a focus on the positional relation between a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit. The structure conceived is such that a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit are provided close to each other so that an RC load between the serial-parallel conversion circuit and the external connection terminal is reduced.

Abstract translation: 提供具有高图像质量和较少终端的显示设备。 本发明的重点是串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子之间的位置关系。 所构想的结构使得串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子彼此靠近地设置，使得串行 - 并行转换电路和外部电路之间的RC负载 连接端子减少。

公开(公告)号：US20150016585A1

公开(公告)日：2015-01-15

申请号：US14315601

申请日：2014-06-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kouhei Toyotaka ,  Jun Koyama ,  Hiroyuki Miyake

IPC: G09G3/36 ,  G11C19/28 ,  H03K3/012 ,  H03K17/687

CPC classification number: H01L27/124 ,  G02F1/1334 ,  G02F1/1337 ,  G02F1/134336 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G3/3275 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0626 ,  G09G2330/021 ,  G11C19/28 ,  G11C19/287 ,  H01L27/1225 ,  H01L29/7869

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

Abstract translation: 半导体器件包括具有相同导电类型的第一和第二晶体管和电路。 第一晶体管的源极和漏极之一与第二晶体管的源极和漏极电连接。 第一和第三电位通过各自的布线提供给电路。 第二电位和第一时钟信号分别被提供给第一和第二晶体管的源极和漏极中的其它电极。 第二个时钟信号被提供给电路。 第三电位高于高于第一电位的第二电位。 第四个电位等于或高于第三个电位。 第一时钟信号交替第二和第四电位，第二时钟信号交替第一和第三电位。 该电路控制第一和第二晶体管的栅极与布线之间的电连接。

公开(公告)号：US20140204073A1

公开(公告)日：2014-07-24

申请号：US14219275

申请日：2014-03-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei Toyotaka ,  Hiroyuki Miyake ,  Ryo Arasawa ,  Koji Kusunoki ,  Tsutomu Murakawa

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/20 ,  G09G3/36 ,  G09G3/3688 ,  G09G2320/103 ,  G09G2330/04

Abstract: Provided is a liquid crystal display device having a pixel including a transistor and a liquid crystal element and a protection circuit electrically connected to one of a source and a drain of the transistor through a data line. The protection circuit includes a first terminal supplied with a first power supply potential and a second terminal supplied with a second power supply potential higher than the first power supply potential. In a moving image display mode, an image signal is input from the data line to the liquid crystal element through the transistor, and the first power supply potential is set at the first potential. In a still image display mode, supply of the image signal is stopped, and the first power supply potential is set at the second potential. The second potential is substantially the same as the minimum value of the image signal.

Abstract translation: 提供一种液晶显示装置，其具有包括晶体管和液晶元件的像素，以及通过数据线电连接到晶体管的源极和漏极之一的保护电路。 保护电路包括提供有第一电源电位的第一端子和被提供有高于第一电源电位的第二电源电位的第二端子。 在运动图像显示模式中，图像信号通过晶体管从数据线输入到液晶元件，并且第一电源电位被设置为第一电位。 在静止图像显示模式下，停止图像信号的供给，将第一电源电位设定为第二电位。 第二电位与图像信号的最小值基本相同。

公开(公告)号：US20130193434A1

公开(公告)日：2013-08-01

申请号：US13799246

申请日：2013-03-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kei Takahashi ,  Kouhei Toyotaka ,  Masashi Tsubuku ,  Kosei Noda ,  Hideaki Kuwabara

IPC: H01L29/26

CPC classification number: H01L29/26 ,  G06K19/07758 ,  G11C7/00 ,  G11C19/28 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Abstract translation: 目的是减少用于LSI，CPU或存储器的晶体管的泄漏电流和寄生电容。 使用薄膜晶体管制造诸如LSI，CPU或存储器的半导体集成电路，其中使用氧化物半导体形成沟道形成区域，该氧化物半导体通过去除作为电子给体的杂质而成为本征或本质上的半导体 （供体），并且具有比硅半导体更大的能隙。 通过使用具有充分降低的氢浓度的高度净化的氧化物半导体层的薄膜晶体管，可以实现由于漏电流而具有低功耗的半导体器件。