公开(公告)号：US07355571B2

公开(公告)日：2008-04-08

申请号：US10515246

申请日：2003-06-09

申请人： Hiroyasu Yamada ,  Manabu Takei

发明人： Hiroyasu Yamada ,  Manabu Takei

IPC分类号： G09G3/30

CPC分类号： G09G3/325 ,  G09G2300/0417 ,  G09G2300/0819 ,  G09G2300/0847 ,  G09G2300/0852 ,  G09G2300/0866 ,  G09G2310/027 ,  G09G2320/0223 ,  G09G2320/043

摘要： A display panel (110) includes a plurality of optical elements (OEL) each having a pair of electrodes and performing an optical operation according to current passing between the pair of electrodes, a current line (DL), a switch circuit (Tr2) that passes a write current (Ia) with a predetermined current value through the current line (DL) during a selection time (Tse) and stops passing current during a nonselection time (Tnse), and a current storage circuit (Tr1, Tr3, Cs, Cp) that stores current data according to the current value of the write current (Ia) passing through the current line (DL) during the selection time (Tse) and that supplies a drive current (Ib) having a current value, which is obtained by subtracting a predetermined offset current (Ioff) from the current value of the stored write current (Ia), to the optical elements (OEL) during the nonselection time (Tnse).

摘要翻译： 显示面板（110）包括多个光学元件（OEL），每个光学元件具有一对电极，并且根据在一对电极之间的电流进行光学操作，电流线（DL），开关电路（Tr 2） 在选择时间（Tse）期间通过当前行（DL）通过具有预定电流值的写入电流（Ia），并且在非选择时间（Tnse）期间停止通过电流，并且当前存储电路（Tr 1，Tr 3 ，Cs，Cp），其根据在选择时间（Tse）期间通过当前行（DL）的写入电流（Ia）的当前值存储当前数据，并且提供具有当前值的驱动电流（Ib） 通过从存储的写入电流（Ia）的当前值减去预定偏移电流（Ioff）而获得，在非选择时间（Tnse）期间将光学元件（OEL）减去。

公开(公告)号：US07157785B2

公开(公告)日：2007-01-02

申请号：US10928927

申请日：2004-08-27

申请人： Manabu Takei ,  Tatsuya Naito ,  Michio Nemoto

发明人： Manabu Takei ,  Tatsuya Naito ,  Michio Nemoto

IPC分类号： H01L27/85 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L31/07

CPC分类号： H02M7/003 ,  H01L29/0696 ,  H01L29/7395 ,  H01L29/872

摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.

摘要翻译： 公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。 提供了使用半导体器件的双向开关器件，并且公开了制造半导体器件的方法。 反向阻断IGBT通过将p型基极区域和发射极电极之间延伸的类型漂移区域1的部分引入肖特基接触来形成反向漏电流和导通电压，形成 肖特基路口。

公开(公告)号：US20060049434A1

公开(公告)日：2006-03-09

申请号：US11219308

申请日：2005-09-02

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L29/80

CPC分类号： H01L29/42356 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396

摘要： A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n−-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

摘要翻译： 半导体器件及其制造方法包括其上选择性地形成氧化物膜的单晶硅衬底。 在氧化膜上形成栅极多晶硅。 栅极多晶硅的表面被栅极氧化膜覆盖，该栅极氧化物膜的表面被杂质浓度高于衬底的n型掺杂的阴极膜覆盖，作为n型 层。 在阴极膜中，与衬底接触的部分成为具有高杂质浓度的n + +缓冲区，接着形成p基区。 在p基区旁边，形成n + SUP源源区。 在阴极膜上，选择性地形成层间绝缘膜，在其上形成发射电极。 以高速率的可接受的产品获得诸如IGBT的半导体器件，具有优异的导通电压到关断损耗折衷和优良的导通电压对击穿电压的折衷。

公开(公告)号：US06610572B1

公开(公告)日：2003-08-26

申请号：US09722927

申请日：2000-11-27

申请人： Manabu Takei ,  Tatsuhiko Fujihira

发明人： Manabu Takei ,  Tatsuhiko Fujihira

IPC分类号： H01L21336

CPC分类号： H01L29/66712 ,  H01L21/263 ,  H01L29/32 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/861

摘要： A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration and a low impurity concentration drift layer, thus achieving both low cost and a high performance. A method for manufacturing a semiconductor device is also provided which can form a high impurity concentration buffer layer and a high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of an active region and an electrode thereof at the right side, to thereby achieve both low cost and high performance.

摘要翻译： 提供了一种半导体器件，其可以通过在晶片工艺中使用便宜的FZ晶片来制造，并且在反面的最外部分的高杂质浓度层和在反面的最外部处以及在相反侧的边界处仍然具有高杂质浓度的尖锐倾斜 高杂质浓度和低杂质浓度漂移层，从而实现低成本和高性能。 还提供了一种用于制造半导体器件的方法，即使在形成有源区和其电极之后，也可以在反面的最外部形成高杂质浓度缓冲层和高杂质浓度层，而没有任何明显的麻烦 在右侧，从而实现低成本和高性能。

公开(公告)号：US20130026560A1

公开(公告)日：2013-01-31

申请号：US13575984

申请日：2011-01-28

申请人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

发明人： Yasuhiko Onishi ,  Mutsumi Kitamura ,  Akio Sugi ,  Manabu Takei

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7813

摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).

摘要翻译： 在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。 平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。 此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

公开(公告)号：US08362980B2

公开(公告)日：2013-01-29

申请号：US13010624

申请日：2011-01-20

申请人： Manabu Takei ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

发明人： Manabu Takei ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

IPC分类号： G09G3/30

CPC分类号： G09G3/325 ,  G09G3/3266 ,  G09G3/3283 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0216 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/027

摘要： A display device includes a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit which applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit which generates gradation current based on a display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit which applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit which controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.

摘要翻译： 显示装置包括具有多个信号线的显示面板和具有包含电流控制型发光装置的多个显示像素的扫描线; 扫描驱动器电路，其将扫描信号施加到每条扫描线，并将连接到扫描线的显示像素设置在选择状态; 信号驱动器电路，其基于显示数据亮度灰度分量生成灰度电流，并提供给以选择状态设置的显示像素; 预充电电路，对每个信号线施加预充电电压，并且以预定的充电状态设置附接到每条扫描线的电容分量; 以及操作控制电路，当电容分量被设定在预定的充电状态时，控制发光器件在非发光状态下的设置。

公开(公告)号：US08339384B2

公开(公告)日：2012-12-25

申请号：US12569322

申请日：2009-09-29

申请人： Manabu Takei ,  Jun Ogura ,  Shunji Kashiyama ,  Tsuyoshi Ozaki

发明人： Manabu Takei ,  Jun Ogura ,  Shunji Kashiyama ,  Tsuyoshi Ozaki

IPC分类号： G06F3/038

CPC分类号： G09G3/3233 ,  G09G3/30 ,  G09G3/3291 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2320/0233 ,  G09G2320/0285 ,  G09G2320/0295 ,  G09G2320/043

摘要： A data acquisition circuit sets one of the potential value at one end of a signal line and the value of a current flown thereto when one end of a current path of a drive device is connected to a light emitting device with the other end thereof set to a potential value where no current flows to the light emitting device. Then the circuit causes current to flow via the current path and the signal line and acquires one of the value of the current flown to the signal line and the potential value at the one end of the signal line according to the set value. A correction operation circuit acquires a threshold voltage and a current amplification factor of the drive device based on one of the current and potential values thus acquired as well as on one of the potential and current values thus set.

摘要翻译： 数据采集​​电路将驱动装置的电流路径的一端连接到发光装置的另一端设定为信号线的一端的电位值中的一方和流过的电流值 没有电流流向发光器件的电位值。 然后，电路使电流通过电流路径和信号线流动，并根据设定值获取流向信号线的电流值和信号线一端的电位值之一。 校正操作电路基于如此获取的电流和电位值之一以及由此设置的电势值和电流值之一获取驱动装置的阈值电压和电流放大系数。

公开(公告)号：US08138542B2

公开(公告)日：2012-03-20

申请号：US12427322

申请日：2009-04-21

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/76 ,  H01L21/20

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US07863151B2

公开(公告)日：2011-01-04

申请号：US12489884

申请日：2009-06-23

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L21/76

CPC分类号： H01L29/66712 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66136 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.

摘要翻译： 用于制造超结半导体器件的制造方法在表现出低电阻的n型半导体衬底上表现出高电阻的n型外延层上形成氧化物膜和氮化物膜。 划线区域中的氮化物膜的部分通过图案化而不被去除，并且通过氮化物膜打开取向标记。 在氧化物膜中打开沟槽图案之后，形成具有高纵横比的沟槽。 去除划线区域外部的氧化膜部分，将p型外延层埋设在沟槽中。 相对于氮化物膜研磨过度生长的p型外延层，通过蚀刻来完成研磨表面，露出n型外延层表面。

公开(公告)号：US07741192B2

公开(公告)日：2010-06-22

申请号：US11208459

申请日：2005-08-19

申请人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

发明人： Kazuo Shimoyama ,  Manabu Takei ,  Haruo Nakazawa

IPC分类号： H01L21/76

CPC分类号： H01L29/7393 ,  H01L21/30608 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L2221/68327 ,  H01L2221/68381

摘要： A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost.

摘要翻译： 形成半导体芯片的上表面结构和底面结构的薄半导体晶片通过双面胶带固定在支撑基板上。 然后，在薄半导体晶片上，通过湿式各向异性蚀刻形成成为划刻线的沟槽，其中晶体面被暴露以形成沟槽的侧壁。 在具有如此露出的晶面的沟槽的侧壁上，通过离子注入和低温退火或激光退火形成用于保持反向击穿电压的隔离层，以便在与...接触的同时延伸到顶表面侧 ap集电极区域作为底面扩散层。 然后，进行激光切割，与集电体区域一起形成在集电极区域上的集电极整齐地切割，而不会在隔离层下方产生任何过量的部分和不足的部分。 此后，从集电极去除双面胶带以制造半导体芯片。 因此可以以低成本形成高度可靠的反向阻挡半导体器件。