公开(公告)号：US4110166A

公开(公告)日：1978-08-29

申请号：US742013

申请日：1976-11-15

申请人： Shigeru Mori ,  Shigeyoshi Ohsawa ,  Hatsuo Aoki ,  Hiroshi Imanaka

发明人： Shigeru Mori ,  Shigeyoshi Ohsawa ,  Hatsuo Aoki ,  Hiroshi Imanaka

IPC分类号： C12P7/42 ,  C07D205/085 ,  C12P1/06 ,  C12P17/10 ,  C12R1/365 ,  C12D9/14

CPC分类号： C12P17/10 ,  C07D205/085 ,  Y10S435/872

摘要： Nocardicin A is produced by culturing a Nocardicin A producing microorganism in a medium containing at least one of shikimic acid, a hydroxy phenyl carboxylic acid, glycine, alanine, serine, homoserine, .alpha.aminobutyric acid, .alpha., .beta.-diaminoproprionic acid and their ester, acid amide and hydrazide derivatives in a concentration of 2-0.001% by weight.

摘要翻译： 通过在含有莽草酸，羟基苯基羧酸，甘氨酸，丙氨酸，丝氨酸，高丝氨酸，α氨基丁酸，α，β-二氨基丙酸及其酯中的至少一种的培养基中培养含有产生诺卡氏菌素A的微生物来产生诺卡氏菌素A， 浓度为2-0.001重量％的酰胺和酰肼衍生物。

公开(公告)号：US08570455B2

公开(公告)日：2013-10-29

申请号：US12934659

申请日：2009-03-30

申请人： Shigeru Mori ,  Isao Shouji ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Isao Shouji ,  Hiroshi Tanabe

IPC分类号： G02F1/136 ,  H01L21/336 ,  H01L21/62 ,  H01L29/66

CPC分类号： H01L29/78621 ,  G02F2001/13685 ,  H01L21/26506 ,  H01L21/26513

摘要： A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.

摘要翻译： 半导体器件包括支撑衬底; 支撑基板上的半导体膜; 半导体膜上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 以及通过将杂质元素引入半导体膜形成的源区和漏区。 半导体膜的厚度在20nm〜40nm的范围内。 在源极区域和沟道形成区域之间以及漏极区域和沟道形成区域之间分别设置有低浓度区域。 低浓度区域的杂质浓度比源极区域和漏极区域的杂质浓度小，并且在支撑衬底侧的下表面侧区域中的杂质浓度小于上表面侧的杂质浓度 对面的区域

公开(公告)号：US08431447B2

公开(公告)日：2013-04-30

申请号：US13291450

申请日：2011-11-08

申请人： Shigeru Mori

发明人： Shigeru Mori

IPC分类号： H01L21/76

CPC分类号： H01L23/28 ,  H01L21/02365 ,  H01L29/02 ,  H01L29/66757 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.

摘要翻译： 提供一种半导体器件，其中半导体层形成在绝缘基板上，其中插入在半导体层和绝缘基板之间的前端绝缘层，其能够防止绝缘基板中包含的杂质对半导体层的作用 并提高半导体器件的可靠性。 在TFT（薄膜晶体管）中，使硼被包含在距离绝缘基板的表面约100nm以下的区域中，使得硼浓度以平均速率降低约1/1000倍/ 1 从绝缘基板的表面朝向半导体层。

公开(公告)号：US20110013107A1

公开(公告)日：2011-01-20

申请号：US12934659

申请日：2009-03-30

申请人： Shigeru Mori ,  Isao Shouji ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Isao Shouji ,  Hiroshi Tanabe

IPC分类号： H01L29/786 ,  H01L31/112 ,  H01L21/336 ,  G02F1/015

CPC分类号： H01L29/78621 ,  G02F2001/13685 ,  H01L21/26506 ,  H01L21/26513

摘要： A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.

摘要翻译： 半导体器件包括支撑衬底; 支撑基板上的半导体膜; 半导体膜上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 以及通过将杂质元素引入半导体膜形成的源区和漏区。 半导体膜的厚度在20nm〜40nm的范围内。 在源极区域和沟道形成区域之间以及漏极区域和沟道形成区域之间分别设置有低浓度区域。 低浓度区域的杂质浓度比源极区域和漏极区域的杂质浓度小，并且在支撑衬底侧的下表面侧区域中的杂质浓度小于上表面侧的杂质浓度 对面的区域

公开(公告)号：US07582933B2

公开(公告)日：2009-09-01

申请号：US11483561

申请日：2006-07-11

申请人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

发明人： Shigeru Mori ,  Takahiro Korenari ,  Tadahiro Matsuzaki ,  Hiroshi Tanabe

IPC分类号： H01L29/772

CPC分类号： H01L29/78621 ,  H01L29/66757

摘要： A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.

摘要翻译： 在绝缘基板上形成基底层，以局部方式形成半导体层。 然后形成栅极绝缘膜以覆盖半导体层，并且栅极电极形成在栅极绝缘膜的一部分上。 然后通过栅极绝缘膜将杂质注入到半导体层中，形成源极区，漏极区和LDD区。 用稀氢氟酸蚀刻栅极绝缘膜。 然后形成电极保护绝缘膜以覆盖栅电极，并且使用稀氢氟酸腐蚀掉电极保护绝缘膜的表面层部分的整个表面。 因此，引入到电极保护绝缘膜和栅极绝缘膜中的载流子阱被去除。

公开(公告)号：US07161774B2

公开(公告)日：2007-01-09

申请号：US11376290

申请日：2006-03-16

申请人： Kazuhiko Hayashi ,  Junichi Fujikata ,  Tsutomu Ishi ,  Shigeru Mori ,  Keishi Ohashi ,  Masafumi Nakada ,  Kiyokazu Nagahara ,  Kunihiko Ishihara ,  Nobuyuki Ishiwata

发明人： Kazuhiko Hayashi ,  Junichi Fujikata ,  Tsutomu Ishi ,  Shigeru Mori ,  Keishi Ohashi ,  Masafumi Nakada ,  Kiyokazu Nagahara ,  Kunihiko Ishihara ,  Nobuyuki Ishiwata

IPC分类号： G11B5/39

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R31/3171 ,  G01R33/093 ,  G11B5/00 ,  G11B5/39 ,  G11B5/3903 ,  G11B5/3909 ,  G11B5/3932 ,  G11B5/3967 ,  H01F10/3268

摘要： A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.

公开(公告)号：US06999287B2

公开(公告)日：2006-02-14

申请号：US10803144

申请日：2004-03-18

申请人： Kazuhiko Hayashi ,  Junichi Fujikata ,  Tsutomu Ishi ,  Shigeru Mori ,  Keishi Ohashi ,  Masafumi Nakada ,  Kiyokazu Nagahara ,  Kunihiko Ishihara ,  Nobuyuki Ishiwata

发明人： Kazuhiko Hayashi ,  Junichi Fujikata ,  Tsutomu Ishi ,  Shigeru Mori ,  Keishi Ohashi ,  Masafumi Nakada ,  Kiyokazu Nagahara ,  Kunihiko Ishihara ,  Nobuyuki Ishiwata

IPC分类号： G11B5/39

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R31/3171 ,  G01R33/093 ,  G11B5/00 ,  G11B5/39 ,  G11B5/3903 ,  G11B5/3909 ,  G11B5/3932 ,  G11B5/3967 ,  H01F10/3268

摘要： A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed immediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.

公开(公告)号：US06934132B2

公开(公告)日：2005-08-23

申请号：US09916529

申请日：2001-07-30

申请人： Kazuhiko Hayashi ,  Junichi Fujikata ,  Tsutomu Ishi ,  Shigeru Mori ,  Keishi Ohashi ,  Masafumi Nakada ,  Kiyokazu Nagahara ,  Kunihiko Ishihara ,  Nobuyuki Ishiwata

发明人： Kazuhiko Hayashi ,  Junichi Fujikata ,  Tsutomu Ishi ,  Shigeru Mori ,  Keishi Ohashi ,  Masafumi Nakada ,  Kiyokazu Nagahara ,  Kunihiko Ishihara ,  Nobuyuki Ishiwata

IPC分类号： G01R31/317 ,  G01R33/09 ,  G11B5/00 ,  G11B5/39 ,  H01F10/32

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R31/3171 ,  G01R33/093 ,  G11B5/00 ,  G11B5/39 ,  G11B5/3903 ,  G11B5/3909 ,  G11B5/3932 ,  G11B5/3967 ,  H01F10/3268

摘要： A magneto-resistance effect head is provided with a lower conductive layer which is provided with a recessed portion, and a vertical bias layer is provided in the recessed portion. A free layer is provided on the lower conductive layer. On the free layer, layered in the following order are the non-magnetic layer, the fixed layer, the fixing layer, and the upper layer so as not to be placed inmediately above the vertical bias layer. The non-magnetic layer, the fixed layer, the fixing layer, and the upper layer are buried in an insulation layer. Furthermore, an upper conductive layer is provided on the upper layer and the insulation layer. In the direction of the magnetic field applied by the vertical bias layer, the free layer is made greater in length than the fixed layer and the free layer is disposed in proximity to the vertical bias layer with the distance between the fixed layer and the vertical bias layer remaining unchanged.

摘要翻译： 磁阻效应头设置有设置有凹部的下导电层，在凹部设置有垂直偏置层。 在下导电层上提供自由层。 在自由层上，按照以下顺序层叠非磁性层，固定层，固定层和上层，以便不立即放置在垂直偏置层上方。 非磁性层，固定层，固定层和上层被埋在绝缘层中。 此外，在上层和绝缘层上设置有上导电层。 在由垂直偏置层施加的磁场的方向上，自由层的长度比固定层长，并且自由层设置在垂直偏置层附近，固定层和垂直偏置之间的距离 层保持不变。

公开(公告)号：US06750537B2

公开(公告)日：2004-06-15

申请号：US09993561

申请日：2001-11-27

申请人： Hideaki Kaino ,  Hiromichi Watanabe ,  Shinichi Sugiura ,  Shuji Kimura ,  Shigeru Mori

发明人： Hideaki Kaino ,  Hiromichi Watanabe ,  Shinichi Sugiura ,  Shuji Kimura ,  Shigeru Mori

IPC分类号： H01L2304

CPC分类号： H05K1/113 ,  H01L2224/48091 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/4623 ,  H05K2201/09436 ,  H01L2924/00014

摘要： A substrate 10 includes multiple layers mounted with a mounted part 20 at its surface. A part pad 40 is provided to the substrate 10 to correspond to an electrode of the mounted part 20. A circuit pattern is provided at a layer at an inner portion of the substrate and an electrically conductive portion 60 for electrically connecting the part pad 40 and the circuit pattern right under the part pad 40.

摘要翻译： 衬底10包括在其表面上安装有安装部件20的多个层。 部件焊盘40设置在基板10上，以对应于安装部分20的电极。电路图案设置在基板的内部的一层和导电部分60，用于将部件焊盘40和 该电路图案位于零件垫40的正下方。

公开(公告)号：US06509528B1

公开(公告)日：2003-01-21

申请号：US09690750

申请日：2000-10-18

申请人： Shigeru Mori ,  Yoshinori Ono

发明人： Shigeru Mori ,  Yoshinori Ono

IPC分类号： H05K103

CPC分类号： H05K1/024 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0195 ,  Y10T29/49126

摘要： A printed circuit board and a manufacturing method thereof can realize a thick film laminated structure of single resin material of low dielectric constant without reinforcement material. The printed circuit board is formed with an insulation layer of composite structure of a first resin material of low dielectric constant and a first general base material having different relative dielectric constants, and the insulation layer is disposed between conductor circuits.

摘要翻译： 印刷电路板及其制造方法可以实现没有增强材料的低介电常数的单一树脂材料的厚膜层压结构。 印刷电路板形成有具有低介电常数的第一树脂材料和具有不同相对介电常数的第一通用基材的复合结构的绝缘层，绝缘层设置在导体电路之间。