公开(公告)号：US20090231921A1

公开(公告)日：2009-09-17

申请号：US12389361

申请日：2009-02-19

申请人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

发明人： Shinichiro Kimura ,  Yasuhiro Shimamoto ,  Digh Hisamoto

IPC分类号： G11C16/06 ,  H01L21/336 ,  H01L29/792 ,  G11C5/14

CPC分类号： H01L27/11568 ,  H01L29/42328 ,  H01L29/792

摘要： In a nonvolatile semiconductor storage device having a split-gate memory cell including a control gate electrode and a sidewall memory gate electrode and a single-gate memory cell including a single memory gate electrode on the same silicon substrate, the control gate electrode is formed in a first region via a control gate insulating film, the sidewall memory gate electrode is formed in the first region via a charge trapping film, and at the same time, a single memory gate electrode is formed in a second region via the charge trapping film. At this time, the sidewall memory gate electrode and the single memory gate electrode are formed in the same process, and the control gate electrode and the sidewall memory gate electrode are formed so as to be adjacently disposed to each other in a state of being electrically isolated from each other.

摘要翻译： 在具有包括控制栅电极和侧壁存储栅电极的分闸存储单元的非易失性半导体存储器件和在同一硅衬底上包括单个存储栅电极的单栅极存储单元中，形成控制栅电极 经由控制栅极绝缘膜的第一区域，所述侧壁存储栅电极经由电荷捕获膜形成在所述第一区域中，并且同时经由电荷捕获膜在第二区域中形成单个存储器栅电极。 此时，侧壁存储器栅极电极和单个存储器栅极电极以相同的工艺形成，并且控制栅极电极和侧壁存储栅电极形成为在电气的状态下彼此相邻地设置 彼此隔离

公开(公告)号：US07504689B2

公开(公告)日：2009-03-17

申请号：US11182013

申请日：2005-07-15

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

摘要翻译： 提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。 根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

公开(公告)号：US20070207581A1

公开(公告)日：2007-09-06

申请号：US11797839

申请日：2007-05-08

申请人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

公开(公告)号：US07259422B1

公开(公告)日：2007-08-21

申请号：US11653832

申请日：2007-01-17

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.

摘要翻译： 存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。 存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。 在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。 形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

公开(公告)号：US07247890B2

公开(公告)日：2007-07-24

申请号：US10931119

申请日：2004-09-01

申请人： Tomoko Sekiguchi ,  Shinichiro Kimura ,  Renichi Yamada ,  Kikuo Watanabe ,  Hiroshi Miki ,  Kenichi Takeda

发明人： Tomoko Sekiguchi ,  Shinichiro Kimura ,  Renichi Yamada ,  Kikuo Watanabe ,  Hiroshi Miki ,  Kenichi Takeda

IPC分类号： H01L31/0328 ,  H01L29/80

CPC分类号： H01L29/66659 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/1079 ,  H01L29/6656 ,  H01L29/7835

摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.

摘要翻译： 这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。 在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射 使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于 电容器。

公开(公告)号：US07235441B2

公开(公告)日：2007-06-26

申请号：US10901347

申请日：2004-07-29

申请人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

发明人： Kan Yasui ,  Digh Hisamoto ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4232 ,  H01L29/792

摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

摘要翻译： 在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。 为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。 此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。 或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

公开(公告)号：US07196368B2

公开(公告)日：2007-03-27

申请号：US10914223

申请日：2004-08-10

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线， 选择线。 由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触， 外围电路区域和存储单元区域之间的台阶高度显着降低。

公开(公告)号：US20060022260A1

公开(公告)日：2006-02-02

申请号：US11182013

申请日：2005-07-15

申请人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

发明人： Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura ,  Tetsuya Ishimaru

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  H01L21/2815 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

公开(公告)号：US06900492B2

公开(公告)日：2005-05-31

申请号：US10164008

申请日：2002-06-07

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/4941 ,  H01L29/6656

摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。 存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。 通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。 此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。 结果，可以以自对准的方式降低硼渗透并形成接触电极。 此外，可以提高构成逻辑电路的MISFET的性能。

公开(公告)号：US06798005B2

公开(公告)日：2004-09-28

申请号：US10206215

申请日：2002-07-29

申请人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

发明人： Shinichiro Kimura ,  Toshiaki Yamanaka ,  Kiyoo Itoh ,  Takeshi Sakata ,  Tomonori Sekiguchi ,  Hideyuki Matsuoka

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/90

摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

摘要翻译： 在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器 ）和埋入布线层（9和11）形成在电容器下面。 由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小， 随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触 （33），外围电路区域和存储单元区域之间的台阶高度显着降低。