公开(公告)号：US08138547B2

公开(公告)日：2012-03-20

申请号：US12548005

申请日：2009-08-26

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78624

Abstract: A semiconductor device is disclosed that includes a silicon-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer. Source extension and drain extension regions are formed in the semiconductor layer. A deep drain region and a deep source region are formed in the semiconductor layer. A first metal-semiconductor alloy contact layer is formed using tilted metal formation at an angle tilted towards the source extension region, such that the source extension region has a metal-semiconductor alloy contact that abuts the substrate from the source side, as a Schottky contact therebetween and the gate shields metal deposition from abutting the deep drain region. A second metal-semiconductor alloy contact is formed located on the first metal-semiconductor layer on each of the source extension region and drain extension region.

Abstract translation: 公开了一种半导体器件，其包括绝缘体上硅衬底，其包括掩埋绝缘体层和上覆半导体层。 在半导体层中形成源延伸和漏扩展区。 在半导体层中形成深漏极区域和深源极区域。 第一金属 - 半导体合金接触层使用倾斜的金属形成，以朝向源延伸区域倾斜的角度形成，使得源极延伸区域具有金属 - 半导体合金接触件，其从源极侧邻接衬底，作为肖特基接触 并且栅极屏蔽金属沉积物抵靠深漏极区域。 在源极延伸区域和漏极延伸区域中的每一个上，在第一金属 - 半导体层上形成第二金属 - 半导体合金接触。

公开(公告)号：US20120043585A1

公开(公告)日：2012-02-23

申请号：US12860977

申请日：2010-08-23

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78 ,  H01L21/335 ,  H01L29/772

CPC classification number: H01L29/78 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66621

Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.

公开(公告)号：US20120007183A1

公开(公告)日：2012-01-12

申请号：US12832829

申请日：2010-07-08

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

Abstract translation: 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

公开(公告)号：US20110121370A1

公开(公告)日：2011-05-26

申请号：US12625827

申请日：2009-11-25

Applicant: Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

Inventor： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

Abstract: A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

Abstract translation: 一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极叠层相邻的衬底的侧壁部分， 应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

公开(公告)号：US07939338B2

公开(公告)日：2011-05-10

申请号：US11128105

申请日：2005-05-11

Applicant: Shan X. Wang ,  Shu-Jen Han

Inventor： Shan X. Wang ,  Shu-Jen Han

IPC: G01R33/00

CPC classification number: G01R33/09 ,  B82Y25/00 ,  G01N33/5438 ,  G01R33/093 ,  G01R33/12 ,  G01R33/1269 ,  Y10T436/13

Abstract: A magnetic sensor array including magnetoresistive sensor elements having outputs combined by frequency division multiplexing (FDM) is provided. Each sensor element provides an input to a mixer which provides a distinct frequency shift. Preferably, time division multiplexing is also used to combine sensor element outputs. Each sensor element is typically in proximity to a corresponding sample. The sensor elements are preferably subarrays having row and column addressable sensor element pixels. This arrangement provides multiple sensor pixels for each sample under test. Multiplexing of sensor element outputs advantageously reduces readout time. A modulated external magnetic field is preferably applied during operation, to reduce the effect of 1/f noise on the sensor element signals. The effect of electromagnetic interference (EMI) induced by the magnetic field on sensor element signals is advantageously reduced by the mixing required for FDM.

Abstract translation: 提供了包括具有通过频分复用（FDM）组合的输出的磁阻传感器元件的磁传感器阵列。 每个传感器元件为混频器提供输入，该混频器提供不同的频移。 优选地，时分复用也用于组合传感器元件输出。 每个传感器元件通常接近相应的样品。 传感器元件优选地是具有行和列可寻址传感器元件像素的子阵列。 这种布置为每个待测样品提供了多个传感器像素。 传感器元件输出的多路复用有利于减少读出时间。 在操作期间优选地施加调制的外部磁场，以减少1 / f噪声对传感器元件信号的影响。 通过FDM所需的混合有利地减少了由磁场引起的电磁干扰（EMI）对传感器元件信号的影响。

公开(公告)号：US09062389B2

公开(公告)日：2015-06-23

申请号：US13618564

申请日：2012-09-14

Applicant: Shu-Jen Han ,  Lian Guo ,  Xuesong Li

Inventor： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC: C25F7/00 ,  C25F5/00 ,  B32B38/10 ,  C25F3/02 ,  C01B31/04

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power supply to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

Abstract translation: 电镀蚀刻装置包括用于输出电流的电源和构造成容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。

公开(公告)号：US08785262B2

公开(公告)日：2014-07-22

申请号：US13610991

申请日：2012-09-12

Applicant: Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78678 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0516 ,  Y10S977/742

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract translation: 提供了自对准碳纳米结构场效应晶体管结构，其使用选择性电介质沉积技术发泡。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。

公开(公告)号：US08680646B2

公开(公告)日：2014-03-25

申请号：US13605529

申请日：2012-09-06

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L29/00

CPC classification number: H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

Abstract: A device and method for device fabrication include forming a buried gate electrode in a dielectric substrate and patterning a stack having a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract translation: 用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅极电极，并且在掩埋栅电极上图案化具有高介电常数层，碳基半导电层和保护层的叠层。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20140076721A1

公开(公告)日：2014-03-20

申请号：US13617727

申请日：2012-09-14

Applicant: Shu-Jen Han ,  Lian Guo ,  Xuesong Li

Inventor： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC: C25F7/00

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

Abstract translation: 电镀蚀刻装置包括输出电流的电力，以及容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。

公开(公告)号：US08610172B2

公开(公告)日：2013-12-17

申请号：US13326825

申请日：2011-12-15

Applicant: Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

Inventor： Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

IPC: H01L29/66

CPC classification number: H01L21/8258 ,  H01L21/823807 ,  H01L27/0605

Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

Abstract translation: 提供在同一CMOS电路内采用不同通道材料的技术。 一方面，制造CMOS电路的方法包括以下步骤。 提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。 第一半导体层凹入第一有源区。 第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。 使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。 使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。