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    Magnetic sensor array having an analog frequency-division multiplexed output
    1.
    发明授权
    Magnetic sensor array having an analog frequency-division multiplexed output 有权
    具有模拟频分复用输出的磁传感器阵列

    公开(公告)号：US07939338B2

    公开(公告)日：2011-05-10

    申请号：US11128105

    申请日：2005-05-11

    Applicant: Shan X. Wang ,  Shu-Jen Han

    Inventor： Shan X. Wang ,  Shu-Jen Han

    IPC: G01R33/00

    CPC classification number: G01R33/09 ,  B82Y25/00 ,  G01N33/5438 ,  G01R33/093 ,  G01R33/12 ,  G01R33/1269 ,  Y10T436/13

    Abstract: A magnetic sensor array including magnetoresistive sensor elements having outputs combined by frequency division multiplexing (FDM) is provided. Each sensor element provides an input to a mixer which provides a distinct frequency shift. Preferably, time division multiplexing is also used to combine sensor element outputs. Each sensor element is typically in proximity to a corresponding sample. The sensor elements are preferably subarrays having row and column addressable sensor element pixels. This arrangement provides multiple sensor pixels for each sample under test. Multiplexing of sensor element outputs advantageously reduces readout time. A modulated external magnetic field is preferably applied during operation, to reduce the effect of 1/f noise on the sensor element signals. The effect of electromagnetic interference (EMI) induced by the magnetic field on sensor element signals is advantageously reduced by the mixing required for FDM.

    Abstract translation: 提供了包括具有通过频分复用（FDM）组合的输出的磁阻传感器元件的磁传感器阵列。 每个传感器元件为混频器提供输入，该混频器提供不同的频移。 优选地，时分复用也用于组合传感器元件输出。 每个传感器元件通常接近相应的样品。 传感器元件优选地是具有行和列可寻址传感器元件像素的子阵列。 这种布置为每个待测样品提供了多个传感器像素。 传感器元件输出的多路复用有利于减少读出时间。 在操作期间优选地施加调制的外部磁场，以减少1 / f噪声对传感器元件信号的影响。 通过FDM所需的混合有利地减少了由磁场引起的电磁干扰（EMI）对传感器元件信号的影响。

    Magnetic Sensor Based Quantitative Binding Kinetics Analysis
    2.
    发明申请
    Magnetic Sensor Based Quantitative Binding Kinetics Analysis 审中-公开
    基于磁传感器的定量结合动力学分析

    公开(公告)号：US20110223612A1

    公开(公告)日：2011-09-15

    申请号：US13046368

    申请日：2011-03-11

    Applicant: Shan X. Wang ,  Richard S. Gaster ,  Liang Xu ,  Shu-Jen Han ,  Robert Wilson

    Inventor： Shan X. Wang ,  Richard S. Gaster ,  Liang Xu ,  Shu-Jen Han ,  Robert Wilson

    IPC: G01N33/557 ,  G01N33/566 ,  G01N33/68 ,  G01N27/72

    CPC classification number: G01N27/745 ,  G01N33/557 ,  Y10T436/143333

    Abstract: Methods for quantitatively determining a binding kinetic parameter of a molecular binding interaction are provided. Aspects of embodiments of the methods include: producing a magnetic sensor device including a magnetic sensor in contact with an assay mixture including a magnetically labeled molecule to produce a detectable molecular binding interaction; obtaining a real-time signal from the magnetic sensor; and quantitatively determining a binding kinetics parameter of the molecular binding interaction from the real-time signal. Also provided are systems and kits configured for use in the methods.

    Abstract translation: 提供了定量测定分子结合相互作用的结合动力学参数的方法。 所述方法的实施方案的方面包括：产生包括与包含磁性标记分子的测定混合物接触以产生可检测分子结合相互作用的磁传感器的磁传感器装置; 从磁传感器获取实时信号; 并从实时信号中定量测定分子结合相互作用的结合动力学参数。 还提供了配置用于该方法的系统和套件。

    Transistor employing vertically stacked self-aligned carbon nanotubes
    6.
    发明授权
    Transistor employing vertically stacked self-aligned carbon nanotubes 有权
    晶体管采用垂直堆叠的自对准碳纳米管

    公开(公告)号：US08895371B2

    公开(公告)日：2014-11-25

    申请号：US13605238

    申请日：2012-09-06

    Applicant: Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

    Inventor： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

    IPC: H01L21/335 ,  H01L51/05 ,  H01L29/775 ,  H01L29/66 ,  H01L51/00 ,  H01L29/12 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/78

    CPC classification number: H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

    Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

    Abstract translation: 形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。 第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。 通过阴离子表面活性剂将负电荷赋予碳纳米管。 静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。 碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。 可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。

    Vertical stacking of carbon nanotube arrays for current enhancement and control
    7.
    发明授权
    Vertical stacking of carbon nanotube arrays for current enhancement and control 有权
    用于当前增强和控制的碳纳米管阵列的垂直堆叠

    公开(公告)号：US08890116B2

    公开(公告)日：2014-11-18

    申请号：US13610089

    申请日：2012-09-11

    Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

    Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

    IPC: H01L29/06 ,  H01L51/00 ,  B82Y10/00 ,  H01L51/05

    CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

    Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

    Abstract translation: 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

    Transistor device with reduced gate resistance
    9.
    发明授权
    Transistor device with reduced gate resistance 有权
    具有降低栅极电阻的晶体管器件

    公开(公告)号：US08642997B2

    公开(公告)日：2014-02-04

    申请号：US13610381

    申请日：2012-09-11

    Applicant: Shu-Jen Han ,  Alberto Valdes Garcia

    Inventor： Shu-Jen Han ,  Alberto Valdes Garcia

    IPC: H01L29/775

    CPC classification number: H01L29/66742 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78636 ,  H01L29/78684

    Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

    Abstract translation: 具有降低的栅极电阻的器件包括具有第一导电部分和形成为与第一导电部分电接触并且横向延伸超过第一导电部分延伸的第二导电部分的栅极结构。 栅极结构嵌入电介质材料中，并且在第一导电部分上具有栅极电介质。 沟道层设置在第一导电部分上。 源极和漏极形成在沟道层的沟道区的相对端部上。 还提供了形成栅极电阻降低的器件的方法。

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