公开(公告)号：US20130285211A1

公开(公告)日：2013-10-31

申请号：US13455732

申请日：2012-04-25

申请人： Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

发明人： Robert J. Gauthier, JR. ,  Jeffrey B. Johnson ,  Junjun Li

IPC分类号： H01L29/00 ,  G06F17/50 ,  H01L21/20

CPC分类号： H01L27/1211 ,  G06F17/5068 ,  H01L21/3086 ,  H01L21/845

摘要： Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material.

摘要翻译： 鳍式场效应晶体管集成电路技术的器件结构，设计结构和制造方法。 构成器件结构的电极的第一和第二鳍片均由第一半导体材料构成。 第二翅片邻近第一翅片形成以限定分隔第一和第二翅片的间隙。 位于间隙中的是由第二半导体材料构成的层。

公开(公告)号：US20120187525A1

公开(公告)日：2012-07-26

申请号：US13012137

申请日：2011-01-24

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L29/12 ,  G06F17/50 ,  H01L21/36

CPC分类号： H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

摘要翻译： 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及横向二极管的设计结构。 器件结构包括位于器件区域中并与阳极和阴极之间的p-n结相交的一个或多个电介质区域，例如STI区域。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。

公开(公告)号：US20090256202A1

公开(公告)日：2009-10-15

申请号：US12102032

申请日：2008-04-14

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L29/786

CPC分类号： H01L27/1203 ,  H01L27/0248

摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

公开(公告)号：US20090160013A1

公开(公告)日：2009-06-25

申请号：US11960030

申请日：2007-12-19

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L29/00 ,  H01L21/4763

CPC分类号： H01L23/34 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

摘要翻译： 半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。 发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。 至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。 或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。 至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。

公开(公告)号：US20130256749A1

公开(公告)日：2013-10-03

申请号：US13431456

申请日：2012-03-27

申请人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

发明人： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Junjun Li

IPC分类号： H01L29/739 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L21/845 ,  H01L27/0262 ,  H01L27/1211

摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

摘要翻译： 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 形成器件结构，其包括器件区域中的第一导电类型的阱和阱中的第二导电性的掺杂区域。 器件区域由绝缘体上半导体衬底的器件层的一部分组成。 掺杂区域和阱的第一部分限定了结。 阱的第二部分位于器件区域的掺杂区域和外部侧壁之间。 可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US20120146150A1

公开(公告)日：2012-06-14

申请号：US12967114

申请日：2010-12-14

申请人： Robert J. Gauthier, JR. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

发明人： Robert J. Gauthier, JR. ,  Mahender Kumar ,  Junjun Li ,  Dustin K. Slisher

IPC分类号： H01L23/62 ,  H01L21/336

CPC分类号： H01L23/60 ,  H01L27/0266 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a self-protected electrostatic discharge field effect transistor (SPESDFET). In the SPESDFET embodiments, a resistance region is positioned laterally between two discrete sections of a deep source/drain region: a first section that is adjacent to the channel region and a second section that is contacted. The second section of the deep source/drain region is silicided, but the first section adjacent to the channel region and the resistance region are non-silicided. Additionally, the gate structure can be either silicided or non-silicided. With such a configuration, the disclosed SPESDFET provides robust ESD protection without consuming additional area and without altering the basic FET design (e.g., without increasing the distance between the deep source/drain regions and the channel region). Also disclosed are embodiments of integrated circuit that incorporates the SPESDFET as an input/output (I/O) pad driver and method embodiments for forming the SPESDFET and the integrated circuit.

摘要翻译： 公开了自保护静电放电场效应晶体管（SPESDFET）的实施例。 在SPESDFET实施例中，电阻区域横向定位在深源极/漏极区域的两个离散部分之间：与沟道区域相邻的第一部分和接触的第二部分。 深源极/漏极区域的第二部分被硅化，但是与沟道区域和电阻区域相邻的第一部分是非硅化的。 另外，栅极结构可以是硅化的或非硅化的。 利用这种配置，所公开的SPESDFET提供强大的ESD保护，而不消耗额外的面积，而不改变基本FET设计（例如，不增加深源/漏区和沟道区之间的距离）。 还公开了将SPESDFET作为输入/输出（I / O）焊盘驱动器和用于形成SPESDFET和集成电路的方法实施例的集成电路的实施例。

公开(公告)号：US20090206367A1

公开(公告)日：2009-08-20

申请号：US12031084

申请日：2008-02-14

申请人： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra

发明人： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L29/7436 ,  H01L27/0259 ,  H01L29/861

摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.

摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

公开(公告)号：US20090086391A1

公开(公告)日：2009-04-02

申请号：US11865820

申请日：2007-10-02

申请人： Robert J. Gauthier, JR. ,  Junjun Li

发明人： Robert J. Gauthier, JR. ,  Junjun Li

IPC分类号： H02H9/00

CPC分类号： H01L27/0285

摘要： An electronic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs and a triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

摘要翻译： 一种用于保护集成电路芯片免受ESD事件的电子放电（ESD）保护电路。 ESD保护电路包括一叠BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及响应于ESD事件触发BigFET栅极驱动器来驱动BigFET的栅极。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

公开(公告)号：US20080308837A1

公开(公告)日：2008-12-18

申请号：US11762811

申请日：2007-06-14

申请人： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher S. Putnam

发明人： Robert J. Gauthier, JR. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher S. Putnam

IPC分类号： H01L29/74 ,  H01L21/20 ,  H01L21/332 ,  H01L21/84 ,  H01L29/00

CPC分类号： H01L27/0262

摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

摘要翻译： 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。

公开(公告)号：US20130141823A1

公开(公告)日：2013-06-06

申请号：US13312047

申请日：2011-12-06

申请人： James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

发明人： James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

IPC分类号： H02H9/04 ,  G06F17/50

CPC分类号： H02H9/046

摘要： Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.

摘要翻译： 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。