公开(公告)号：US07498640B2

公开(公告)日：2009-03-03

申请号：US10437930

申请日：2003-05-15

申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Guy Moshe Cohen ,  Kathryn Wilder Guarini ,  Christian Lavoie ,  Paul Michael Solomon ,  Ying Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6653 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66507 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a silicon layer over the metal layer, etching anisotropically and selectively with respect to the metal the silicon layer, reacting the metal with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

公开(公告)号：US07449782B2

公开(公告)日：2008-11-11

申请号：US10838378

申请日：2004-05-04

申请人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral, Jr. ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L29/40

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20080274611A1

公开(公告)日：2008-11-06

申请号：US12136885

申请日：2008-06-11

申请人： Cyril Cabral ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

发明人： Cyril Cabral ,  Michael A. Cobb ,  Asa Frye ,  Balasubramanian S. Pranatharthi Haran ,  Randolph F. Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew P. Mansson ,  Renee T. Mo ,  Jay W. Strane ,  Horatio S. Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 然后执行退火步骤A选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US20080246120A1

公开(公告)日：2008-10-09

申请号：US12120854

申请日：2008-05-15

申请人： Cyril Cabral ,  Roy A. Carruthers ,  Jia Chen ,  Christophe Detavernier ,  James M. Harper ,  Christian Lavoie

发明人： Cyril Cabral ,  Roy A. Carruthers ,  Jia Chen ,  Christophe Detavernier ,  James M. Harper ,  Christian Lavoie

IPC分类号： H01L29/161

CPC分类号： H01L21/28518

摘要： A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

摘要翻译： 提供了一种解决在锗原子存在下形成二硅化钴期间显示的增加的成核温度的方法。 硅化物形成温度的降低通过首先提供包括至少包含Ni的Co层作为添加元素在包含SiGe的衬底的顶部上的结构来实现。 接下来，对该结构进行自对准硅化物工艺，其包括第一退火，选择性蚀刻步骤和第二退火，以在含SiGe的衬底上形成（Co，Ni）二硅化物的固溶体。 至少包括Ni的Co层可以包括Co和Ni的合金层，Ni / Co的堆叠或Co / Ni的堆叠。 还提供了包含（Co，Ni）二硅化物在含SiGe的衬底上的固溶体的半导体结构。

公开(公告)号：US20080227283A1

公开(公告)日：2008-09-18

申请号：US12108001

申请日：2008-04-23

申请人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L21/28

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming gennano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种在与由纯金属形成的常规硅化物接触相比更耐蚀刻性的Ge含有层上方形成硅锗化物的方法。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20070254478A1

公开(公告)日：2007-11-01

申请号：US11380528

申请日：2006-04-27

申请人： Zhijiong Luo ,  William Henson ,  Christian Lavoie ,  Huilong Zhu

发明人： Zhijiong Luo ,  William Henson ,  Christian Lavoie ,  Huilong Zhu

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.

摘要翻译： 一种用于制造硅化物栅极场效应晶体管的方法，包括：在形成硅化物栅极之前，通过使接触含硅栅极的金属硅化物形成金属层退火来掩蔽硅源/漏极区。 硅化物栅极可以是完全硅化的栅极或部分硅化的栅极。 在去掩蔽源/漏区之后，可以在源极/漏极区上形成硅化物层，并且还可以在部分硅化物栅极上形成硅化物层。 第二硅化物层和部分硅化物栅极还提供完全硅化的栅极。

公开(公告)号：US20070249149A1

公开(公告)日：2007-10-25

申请号：US11379651

申请日：2006-04-21

申请人： Sadanand Deshpande ,  Jay Strane ,  Michael Belyansky ,  Christian Lavoie

发明人： Sadanand Deshpande ,  Jay Strane ,  Michael Belyansky ,  Christian Lavoie

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/3221 ,  H01L21/76829 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The use of nickel, Ni, based alloys that enables higher contact module which, in turn, provides the device designers additional gains in transistor speeds is provided. Specifically, the use of Ni based alloys for silicide formation in 90 nm technologies and beyond enables higher temperature (greater than 450° C.) processing in the contact module for advanced devices. This capability of higher thermal budget in processing stress inducing films in the contact module helps enhance device performance beyond what is possible with conventional pure Ni based silicides. Another benefit of this application is the deposition temperature of the contact dielectric (e.g., pre-metal dielectric) can be increased to enable moisture free, denser, higher quality films.

摘要翻译： 提供使用能够实现更高接触模块的镍，镍基合金，这又提供了器件设计器在晶体管速度方面的额外增益。 具体来说，使用Ni基合金在90nm以上的技术中进行硅化物形成，可以实现高级器件接触模块的高温（大于450°C）的加工。 在接触模块中处理应力诱导膜时，这种具有较高热预算的能力有助于提高器件性能，超出传统纯Ni基硅化物的可能性。 该应用的另一个好处是可以增加接触电介质的沉积温度（例如，预金属电介质），以实现无水分，更致密，更高质量的膜。

公开(公告)号：US07102234B2

公开(公告)日：2006-09-05

申请号：US10827064

申请日：2004-04-19

申请人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

发明人： Cyril Cabral, Jr. ,  Roy Arthur Carruthers ,  James McKell Edwin Harper ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Yun Yu Wang

IPC分类号： H01L23/48 ,  H01L29/40

CPC分类号： H01L21/28518

摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.

摘要翻译： 一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自 由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层 金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。 当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相 的Ni硅化物。

公开(公告)号：US06989322B2

公开(公告)日：2006-01-24

申请号：US10707175

申请日：2003-11-25

申请人： Oleg G. Gluschenkov ,  Cyril Cabral, Jr. ,  Omer Dokumaci ,  Christian Lavoie

发明人： Oleg G. Gluschenkov ,  Cyril Cabral, Jr. ,  Omer Dokumaci ,  Christian Lavoie

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide and the channel.

摘要翻译： 通过使用薄硅化停止扩展来形成MOSFET器件中的非常低的电阻，其既用作硅化“阻挡”势垒，又作为源/漏硅化物区域和MOSFET的沟道区之间的薄界面层。 通过作为硅化停止，硅化 - 停止扩展限制硅化，并且不被源/漏硅化物破坏。 这允许在硅化物和沟道之间形成非常薄的，高掺杂的硅化 - 停止延伸，在硅化物和沟道之间提供基本理想的低串联电阻接口。

公开(公告)号：US06987050B2

公开(公告)日：2006-01-17

申请号：US09902483

申请日：2001-07-11

申请人： Cyril Cabral, Jr. ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Paul Michael Solomon

发明人： Cyril Cabral, Jr. ,  Kevin Kok Chan ,  Guy Moshe Cohen ,  Christian Lavoie ,  Ronnen Andrew Roy ,  Paul Michael Solomon

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/66772 ,  H01L21/28518 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/78

摘要： A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

摘要翻译： 一种用于制造半导体器件用硅化物的方法（及其结构）包括在硅衬底上沉积金属或其合金，使金属或合金反应形成第一硅化物相，蚀刻任何未反应的金属，沉积硅 在第一硅化物相上，使硅帽层反应形成第二硅化物相，并且蚀刻任何未反应的硅。 衬底可以是绝缘体上硅（SOI）衬底或体硅衬底。