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    Nonvolatile Memory Devices, Read Methods Thereof And Memory Systems Including The Nonvolatile Memory Devices
    43.
    发明申请
    Nonvolatile Memory Devices, Read Methods Thereof And Memory Systems Including The Nonvolatile Memory Devices 有权
    非易失性存储器件，其读取方法和包括非易失性存储器件的存储器系统

    公开(公告)号：US20110317489A1

    公开(公告)日：2011-12-29

    申请号：US13093320

    申请日：2011-04-25

    申请人： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

    发明人： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

    IPC分类号： G11C16/26

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11582

    摘要： Reading methods of nonvolatile memory devices including a substrate and a plurality of memory cells which are stacked in a direction intersecting the substrate. The reading methods apply a bit line voltage to a plurality of bit lines and apply a first string selection line voltage to at least one selected string selection line. The reading methods apply a second string selection line voltage to at least one unselected string selection line and apply a read voltage to a plurality of word lines. The reading methods apply a first ground selection line voltage to at least one selected ground selection line and apply a second ground selection line voltage to at least one unselected ground selection line.

    摘要翻译： 非易失性存储器件的读取方法包括在与衬底交叉的方向上堆叠的衬底和多个存储单元。 读取方法将位线电压施加到多个位线，并将第一串选择线电压施加到至少一个所选择的串选择线。 读取方法将第二串选择线电压施加到至少一个未选择的串选择线，并将读电压施加到多个字线。 读取方法将第一接地选择线电压施加到至少一个所选择的接地选择线，并将第二接地选择线电压施加到至少一个未选择的接地选择线。

    Three-dimensional semiconductor memory device and a method of fabricating the same
    45.
    发明授权
    Three-dimensional semiconductor memory device and a method of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08409977B2

    公开(公告)日：2013-04-02

    申请号：US12858057

    申请日：2010-08-17

    申请人： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmi Hwang ,  Wonseok Cho ,  Jinsoo Lim

    发明人： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmi Hwang ,  Wonseok Cho ,  Jinsoo Lim

    IPC分类号： H01L21/8229

    CPC分类号： H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

    摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each recess region.

    摘要翻译： 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，并且形成导电体 每个凹陷区域内的图案。

    Nonvolatile memory devices, erasing methods thereof and memory systems including the same
    48.
    发明授权
    Nonvolatile memory devices, erasing methods thereof and memory systems including the same 有权
    非易失性存储器件，其擦除方法和包括其的存储器系统

    公开(公告)号：US08873294B2

    公开(公告)日：2014-10-28

    申请号：US13295335

    申请日：2011-11-14

    申请人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

    发明人： Sunil Shim ,  Jaehoon Jang ,  Jungdal Choi ,  Woonkyung Lee ,  Kihyun Kim

    IPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  H01L29/792 ,  G11C16/30 ,  H01L27/115

    CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    摘要： Provided are erase methods for a memory device which includes a substrate and multiple cell strings provided on the substrate, each cell string including multiple cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the cell strings; applying a ground voltage to string selection lines connected with selection transistors of the cell strings; applying a word line erase voltage to word lines connected with memory cells of the cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage.

    摘要翻译： 提供了一种存储器件的擦除方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个单元晶体管。 所述擦除方法包括将地电压施加到与所述电池串的地选择晶体管连接的接地选择线; 将接地电压施加到与电池串的选择晶体管连接的串选择线; 对与单元串的存储单元连接的字线施加字线擦除电压; 向基板施加擦除电压; 响应于施加所述擦除电压来控制所述接地选择线的电压; 以及响应于施加所述擦除电压来控制所述串选择线的电压。

    Operating method of nonvolatile memory device
    49.
    发明授权
    Operating method of nonvolatile memory device 有权
    非易失性存储器件的操作方法

    公开(公告)号：US08576629B2

    公开(公告)日：2013-11-05

    申请号：US13315523

    申请日：2011-12-09

    申请人： Byeong-In Choe ,  Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang

    发明人： Byeong-In Choe ,  Sunil Shim ,  Woonkyung Lee ,  Jaehoon Jang

    IPC分类号： G11C11/34

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  H01L27/11582

    摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.

    摘要翻译： 公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。 对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线 多个第一选择线。

    Operating Methods of Nonvolatile Memory Devices
    50.
    发明申请
    Operating Methods of Nonvolatile Memory Devices 有权
    非易失性存储器件的操作方法

    公开(公告)号：US20130182502A1

    公开(公告)日：2013-07-18

    申请号：US13784969

    申请日：2013-03-05

    申请人： Byeong-in Cheo ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim ,  Woonkyung Lee

    发明人： Byeong-in Cheo ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim ,  Woonkyung Lee

    IPC分类号： G11C16/14 ,  G11C7/14

    CPC分类号： G11C16/14 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed are methods of operating a nonvolatile memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings; floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

    摘要翻译： 公开了一种非易失性存储器件的操作方法，其包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。 所述方法可以包括将字线擦除电压施加到连接到所述多个单元串的存储单元的字线; 连接到多个单元串的接地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。