公开(公告)号：US20180151463A1

公开(公告)日：2018-05-31

申请号：US15361390

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L21/768

Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.

公开(公告)号：US09517938B2

公开(公告)日：2016-12-13

申请号：US14791650

申请日：2015-07-06

Applicant: Texas Instruments Incorporated

Inventor： James Cooper Wainerdi ,  Robert Reid Doering ,  Luigi Colombo

IPC: B03C1/00 ,  C01B31/02 ,  B03C1/005 ,  B03C1/033 ,  B03C1/035 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: C01B31/0266 ,  B03C1/005 ,  B03C1/0335 ,  B03C1/035 ,  B03C2201/20 ,  B03C2201/22 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  C01B2202/02 ,  C01B2202/22 ,  Y10S977/751 ,  Y10S977/845

Abstract: A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.

Abstract translation: 通过将SWNTs置于稀释流体中来分离来自半导体类型的金属单壁碳纳米管（SWNT）的过程，将SWNT暴露于偶极诱导磁场，其诱导SWNT中的磁偶极子，使得偶极子的强度取决于 包含偶极子的SWNT的导电性，定向金属SWNT，并将SWNT暴露于具有空间梯度的磁场，使得定向金属SWNT在磁场梯度中漂移，从而与半导体SWNT空间分离。 公开了一种用于排序SWNT的过程的设备。

公开(公告)号：US09114995B2

公开(公告)日：2015-08-25

申请号：US14305119

申请日：2014-06-16

Applicant: Texas Instruments Incorporated

Inventor： James Cooper Wainerdi ,  Robert Reid Doering ,  Luigi Colombo

IPC: B03C1/30 ,  C01B31/02 ,  B03C1/005 ,  B03C1/033

CPC classification number: C01B31/0266 ,  B03C1/005 ,  B03C1/0335 ,  B03C1/035 ,  B03C2201/20 ,  B03C2201/22 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  C01B2202/02 ,  C01B2202/22 ,  Y10S977/751 ,  Y10S977/845

Abstract: A process of sorting metallic single wall carbon nanotubes (SWNTs) from semiconducting types by disposing the SWNTs in a dilute fluid, exposing the SWNTs to a dipole-inducing magnetic field which induces magnetic dipoles in the SWNTs so that a strength of a dipole depends on a conductivity of the SWNT containing the dipole, orienting the metallic SWNTs, and exposing the SWNTs to a magnetic field with a spatial gradient so that the oriented metallic SWNTs drift in the magnetic field gradient and thereby becomes spatially separated from the semiconducting SWNTs. An apparatus for the process of sorting SWNTs is disclosed.

Abstract translation: 通过将SWNTs置于稀释流体中来分离来自半导体类型的金属单壁碳纳米管（SWNT）的过程，将SWNT暴露于偶极诱导磁场，其诱导SWNT中的磁偶极子，使得偶极子的强度取决于 包含偶极子的SWNT的导电性，定向金属SWNT，并将SWNT暴露于具有空间梯度的磁场，使得定向金属SWNT在磁场梯度中漂移，从而与半导体SWNT空间分离。 公开了一种用于排序SWNT的过程的设备。

公开(公告)号：US20250066526A1

公开(公告)日：2025-02-27

申请号：US18942875

申请日：2024-11-11

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08J5/00 ,  C08K3/04 ,  C08K3/08 ,  C08K7/00 ,  C08L25/06 ,  C08L33/12 ,  G03F1/78

Abstract: A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

公开(公告)号：US20230307312A1

公开(公告)日：2023-09-28

申请号：US18143446

申请日：2023-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L23/3733 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US11676880B2

公开(公告)日：2023-06-13

申请号：US15361399

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3733 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US11670671B2

公开(公告)日：2023-06-06

申请号：US17181485

申请日：2021-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

CPC classification number: H01L28/40 ,  H01G4/085 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/0629 ,  H01L29/0649

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US11254775B2

公开(公告)日：2022-02-22

申请号：US16229971

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08L33/12 ,  C08K3/08 ,  C08K7/00 ,  C08J5/24 ,  G03F1/78 ,  C08K3/04 ,  C08J5/00 ,  C08L25/06

Abstract: A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

公开(公告)号：US20210118762A1

公开(公告)日：2021-04-22

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US10964778B2

公开(公告)日：2021-03-30

申请号：US15902764

申请日：2018-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.