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公开(公告)号：US11940826B2
公开(公告)日：2024-03-26
申请号：US17572692
申请日：2022-01-11
Applicant: Texas Instruments Incorporated
Inventor： Sachin Sudhir Turkewadikar , Nitin Agarwal , Madhan Radhakrishnan
CPC classification number: G05F1/56 , H02M1/0045 , G01R31/2813 , H02M3/158
Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
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公开(公告)号：US11894817B2
公开(公告)日：2024-02-06
申请号：US18175828
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Suresh Mallala , Nitin Agarwal
CPC classification number: H03F3/45192 , H03F3/3066 , H03F2200/372 , H03F2203/45248
Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.
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公开(公告)号：US20230155553A1
公开(公告)日：2023-05-18
申请号：US18155261
申请日：2023-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Karanjkar , Venkata Ramanan
CPC classification number: H03F1/0211 , H03F3/45197 , H03M1/66 , H03F2203/45044 , H03F2200/375
Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.
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公开(公告)号：US11626841B2
公开(公告)日：2023-04-11
申请号：US17136427
申请日：2020-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Aniruddha Roy
Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.
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45.发明授权公开(公告)号：US11437955B1
公开(公告)日：2022-09-06
申请号：US17510032
申请日：2021-10-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Aniruddha Roy , Preetham Narayana Reddy
Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.
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Patent Agency Ranking
公开(公告)号：US20210226619A1
公开(公告)日：2021-07-22
申请号：US17223097
申请日：2021-04-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R.
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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公开(公告)号：US11070180B2
公开(公告)日：2021-07-20
申请号：US16395334
申请日：2019-04-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Aniruddha Roy
Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.
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公开(公告)号：US20200321952A1
公开(公告)日：2020-10-08
申请号：US16378526
申请日：2019-04-08
Applicant: Texas Instruments Incorporated
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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公开(公告)号：US20200057106A1
公开(公告)日：2020-02-20
申请号：US16538518
申请日：2019-08-12
Applicant: Texas Instruments Incorporated
Inventor： Lakshmanan Balasubramanian , Nadeem Husain Tehsildar , Rubin Ajit Parekhji , Suresh Mallala , Nitin Agarwal
IPC: G01R31/3183 , G01R31/3167 , H03M1/10 , G06F17/50
Abstract: In one embodiment, a method of operating a computational system to evaluate a device under test, where the device under test is operable to receive a digital code input and output in response a corresponding output. The method injects a plurality of simulated faults into a pre-silicon model of the device under test. For each injected simulated fault, the method inputs a plurality of digital codes to the model. For each input digital code, the method selectively stores the input digital code if a difference, between a corresponding output for the input digital code and a no-fault output for the input, exceeds a predetermined threshold value.
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公开(公告)号：US10534387B2
公开(公告)日：2020-01-14
申请号：US15710883
申请日：2017-09-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sachin Sudhir Turkewadikar , Nitin Agarwal , Madhan Radhakrishnan
Abstract: A power control integrated circuit (IC) chip can include a direct current (DC)-DC converter that outputs a switching voltage in response to a switching output enable signal. The power control IC chip can also include an inductor detect circuit that detects whether an inductor is conductively coupled to the DC-DC converter and a powered circuit component in response to an inductor detect signal. The power control IC chip can further include control logic that (i) controls the inductor detect signal based on an enable DC-DC signal and (ii) controls the switching output enable signal provided to the DC-DC converter and a linear output disable signal provided to a linear regulator based on a signal from the inductor detect circuit indicating whether the inductor is conductively coupled to the DC-DC converter and the powered circuit component.
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