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    Communication system and method
    42.
    发明授权
    Communication system and method 有权
    通信系统及方法

    公开(公告)号：US09490967B1

    公开(公告)日：2016-11-08

    申请号：US14978363

    申请日：2015-12-22

    Applicant: Texas Instruments Incorporated

    Inventor： Robert Floyd Payne

    IPC: H04L5/20 ,  H04L7/027 ,  H04L25/02 ,  H04L1/00 ,  H04L7/00 ,  H04L25/14

    CPC classification number: H04L25/0272 ,  G06F13/38 ,  H04L1/0045 ,  H04L7/0008 ,  H04L7/0066 ,  H04L25/4917

    Abstract: A communication system includes a receiver for decoding data having three states of −1, 0, and 1. The receiver includes a first input coupled to a first data line, a second input coupled to a second data line, and a third input coupled to a third data line. A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line. A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines.

    Abstract translation: 通信系统包括用于解码具有三个状态-1,0和1的数据的接收器。接收机包括耦合到第一数据线的第一输入，耦合到第二数据线的第二输入和耦合到第二数据线的第三输入 第三条数据线。 第一比较器耦合到第一输出，其中第一比较器用于响应于第一数据线上的电压的符号减去第二数据线上的电压来产生数据信号。 第二比较器耦合到第二输出，其中第二比较器用于响应于第三数据线上的电压的符号减去第一和第二数据线上的电压的平均来产生时钟信号。

    Embedded clock in a communication system
    48.
    发明授权
    Embedded clock in a communication system 有权

    公开(公告)号：US10528075B2

    公开(公告)日：2020-01-07

    申请号：US16195275

    申请日：2018-11-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Floyd Payne

    IPC: H04B1/16 ,  H04B1/04 ,  H04L25/49 ,  G06F1/04

    Abstract: Transmitter circuitry transmits: a first voltage as the return-to-zero signal that is higher than a first positive threshold, the first voltage being decodable to a first order of data bits; a second voltage as a return-to-zero signal that is between a second positive threshold and the first positive threshold, the second voltage being decodable to a second order of the data bits, and the second positive threshold being lower than the first positive threshold; a third voltage as the return-to-zero signal that is between a first negative threshold and a second negative threshold, the third voltage being decodable to a third order of the data bits, and the second negative threshold being higher than the first negative threshold; and a fourth voltage as the return-to-zero signal that is lower than the first negative threshold, the fourth voltage being decodable to a fourth order of the data bits. Clock circuitry transitions a clock signal for the return-to-zero signal crossing the second positive threshold, and for the return-to-zero signal crossing the second negative threshold.

    Embedded clock in digital communication system
    49.
    发明授权
    Embedded clock in digital communication system 有权

    公开(公告)号：US10411876B2

    公开(公告)日：2019-09-10

    申请号：US15832836

    申请日：2017-12-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Floyd Payne

    IPC: H04L5/00 ,  H04L7/027 ,  H04L25/02 ,  H04L1/00 ,  H04L7/00 ,  H04L25/14 ,  H03M9/00

    Abstract: A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

    DIGITAL CLOCK DUTY CYCLE CORRECTION
    50.
    发明申请
    DIGITAL CLOCK DUTY CYCLE CORRECTION 审中-公开

    公开(公告)号：US20190267979A1

    公开(公告)日：2019-08-29

    申请号：US16410508

    申请日：2019-05-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K5/156 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

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