公开(公告)号：US20250079340A1

公开(公告)日：2025-03-06

申请号：US18951320

申请日：2024-11-18

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.

公开(公告)号：US12148717B2

公开(公告)日：2024-11-19

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US12033936B2

公开(公告)日：2024-07-09

申请号：US17963149

申请日：2022-10-10

Applicant: Texas Instruments Incorporated

Inventor： Klaas De Haan ,  Mikhail Valeryevich Ivanov ,  Tobias Bernhard Fritz ,  Swaminathan Sankaran ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L21/50 ,  H01L23/50 ,  H04L25/02

CPC classification number: H01L23/5227 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5222 ,  H04L25/0268

Abstract: An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

公开(公告)号：US20240120270A1

公开(公告)日：2024-04-11

申请号：US18527618

申请日：2023-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/58

CPC classification number: H01L23/5223 ,  H01L23/5227 ,  H01L23/585

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

公开(公告)号：US20240113094A1

公开(公告)日：2024-04-04

申请号：US17957847

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Sreeram N. S. ,  Kashyap Barot ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L25/18 ,  H01F27/28 ,  H01F27/29 ,  H01F27/32 ,  H01L23/00 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/323 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/01 ,  H01F2027/2809 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/4809 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/4909

Abstract: A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.

公开(公告)号：US11784212B2

公开(公告)日：2023-10-10

申请号：US17007726

申请日：2020-08-31

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L23/522 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0292

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US20230047044A1

公开(公告)日：2023-02-16

申请号：US17403723

申请日：2021-08-16

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Stewart Costner ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L49/02 ,  H01G4/30 ,  H01L29/06

Abstract: A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.

公开(公告)号：US20220209750A1

公开(公告)日：2022-06-30

申请号：US17223792

申请日：2021-04-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Swaminathan Sankaran ,  Brad Kramer ,  Thomas Dyer Bonifield

IPC: H03H11/02 ,  H01L27/01 ,  H01L27/06

Abstract: An integrated circuit includes a substrate, a reference contact coupled to the substrate, a capacitor over the substrate, and a substrate element. The capacitor includes a first conductive element having an associated parasitic capacitance and a second conductive element electrically isolated from the first conductive element. The substrate element is coupled to the first conductive element by the parasitic capacitance and coupled to the reference contact. The substrate element includes a conductive doped region in the substrate and aligned with the first conductive element and the reference contact.

公开(公告)号：US20220181240A1

公开(公告)日：2022-06-09

申请号：US17679065

申请日：2022-02-23

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/64 ,  H01L49/02 ,  H01L25/065 ,  H01L25/00

Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.

公开(公告)号：US11222945B2

公开(公告)日：2022-01-11

申请号：US15857778

申请日：2017-12-29

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Kannan Soundarapandian

IPC: H01L21/60 ,  H01L29/06 ,  H01L49/02 ,  H01G4/012 ,  H01G4/08 ,  H01L21/283 ,  H01L21/02 ,  H01L21/762 ,  H01L23/528 ,  H01L23/522 ,  H01L23/60 ,  H01G4/30 ,  H01L21/768 ,  H01L23/532 ,  H01L27/06 ,  H01L23/00

Abstract: Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.