公开(公告)号：US20210074683A1

公开(公告)日：2021-03-11

申请号：US17099365

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/552 ,  H01L21/3205 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

公开(公告)号：US20210043581A1

公开(公告)日：2021-02-11

申请号：US17079704

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

公开(公告)号：US10916488B2

公开(公告)日：2021-02-09

申请号：US16431747

申请日：2019-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Szu-Wei Lu

IPC: H01L23/40 ,  H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L25/18 ,  H01L23/31

Abstract: Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.

公开(公告)号：US10910267B2

公开(公告)日：2021-02-02

申请号：US16908348

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L21/768 ,  H01L23/544 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  H01L23/498

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

公开(公告)号：US20200350280A1

公开(公告)日：2020-11-05

申请号：US16934631

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chuan Chang ,  Tsei-Chung Fu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31

Abstract: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.

公开(公告)号：US20200294936A1

公开(公告)日：2020-09-17

申请号：US16887351

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/03 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die.

公开(公告)号：US10515904B2

公开(公告)日：2019-12-24

申请号：US16229021

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: Methods for forming chip package structures are provided. The method includes disposing a first chip structure, a second chip structure over a carrier substrate and forming a molding compound layer surrounding the first chip structure and the second chip structure. The method includes forming a dielectric structure over the molding compound layer and a first grounding line in the dielectric structure and cutting the first grounding line to form a first end enlarged portion of the first grounding line. In addition, the first end enlarged portion has a gradually increased thickness.

公开(公告)号：US10510732B2

公开(公告)日：2019-12-17

申请号：US15854755

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Ju Tsou ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Pu Wang ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.

公开(公告)号：US10438934B1

公开(公告)日：2019-10-08

申请号：US15979494

申请日：2018-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Chin-Fu Kao ,  Jing-Cheng Lin ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2

公开(公告)号：US10340247B2

公开(公告)日：2019-07-02

申请号：US15705894

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L27/06

Abstract: A method for forming a semiconductor device structure and method for forming the same are provided. The method includes hybrid bonding a first wafer and a second wafer to form a hybrid bonding structure, and the hybrid bonding structure comprises a metallic bonding interface and a polymer-to-polymer bonding structure. The method includes forming at least one through-substrate via (TSV) through the second wafer, and the TSV extends from a bottom surface of the second wafer to a top surface of the first wafer.