公开(公告)号：US20170278744A1

公开(公告)日：2017-09-28

申请号：US15178229

申请日：2016-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L29/43 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/532 ,  H01L21/311 ,  H01L29/08

CPC classification number: H01L21/76816 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/435

Abstract: A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.

公开(公告)号：US20240355730A1

公开(公告)日：2024-10-24

申请号：US18761397

申请日：2024-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC: H01L23/522 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L28/24

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US20240250139A1

公开(公告)日：2024-07-25

申请号：US18438575

申请日：2024-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Yu-Feng Yin ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Chen-Yuan Kao

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L21/28026 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

公开(公告)号：US20220384244A1

公开(公告)日：2022-12-01

申请号：US17815975

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pang-Sheng Chang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Li-Chieh Wu ,  Chun-Wei Hsu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

公开(公告)号：US11508822B2

公开(公告)日：2022-11-22

申请号：US16899140

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L29/04 ,  H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.

公开(公告)号：US20220359399A1

公开(公告)日：2022-11-10

申请号：US17874804

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Che Lin ,  Po-Yu Huang ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang ,  Rueijer Lin ,  Wei-Jung Lin ,  Chen-Yuan Kao

IPC: H01L23/535 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/285 ,  H01L23/48

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

公开(公告)号：US11348830B2

公开(公告)日：2022-05-31

申请号：US17114174

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Hsien-Cheng Wang ,  Mei-Yun Wang

IPC: H01L21/768 ,  H01L21/311 ,  H01L29/43 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L23/485

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

公开(公告)号：US20220139828A1

公开(公告)日：2022-05-05

申请号：US17648138

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3115

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US20210257248A1

公开(公告)日：2021-08-19

申请号：US16944876

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pang-Sheng Chang ,  Chao-Hsun Wang ,  Kuo-YI Chao ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Li-Chieh Wu ,  Chun-Wei Hsu

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

公开(公告)号：US20210118801A1

公开(公告)日：2021-04-22

申请号：US16656614

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Hsun Wang ,  Wang-Jung Hsueh ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Ru-Gun Liu

IPC: H01L23/535 ,  H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/532 ,  H01L21/74 ,  H01L21/768

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.