公开(公告)号：US10192987B2

公开(公告)日：2019-01-29

申请号：US15665395

申请日：2017-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A fin-type field effect transistor comprising a substrate, a plurality of insulators, at least one gate stack and strained material portions is described. The substrate has a plurality of fins thereon and the fin comprises a stop layer embedded therein. The plurality of insulators is disposed on the substrate and between the plurality of fins. The at least one gate stack is disposed over the plurality of fins and on the plurality of insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

公开(公告)号：US10109627B2

公开(公告)日：2018-10-23

申请号：US15063907

申请日：2016-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han Lin ,  Che-Cheng Chang ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device is provided. The method may include steps of receiving a device that includes a source/drain, a gate, a gate spacer formed on a sidewall of the gate, and a dielectric component formed over the source/drain, forming a recess in a top surface of the dielectric component; forming a dielectric layer over the top surface of the dielectric component and over the recess, such that a portion of the dielectric layer assumes a recessed shape; and etching a contact hole through the dielectric layer and the dielectric component, the contact hole exposing the source/drain.

公开(公告)号：US20180240895A1

公开(公告)日：2018-08-23

申请号：US15959298

申请日：2018-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor device including a first fin field effect transistor and a second fin field effect transistor is provided. The first fin field effect transistor includes a first semiconductor channel, a first gate overlapped with the first semiconductor channel, a first dielectric layer disposed between the first semiconductor channel and the first gate, and a pair of first spacers disposed on sidewalls of the first gate. The second fin field effect transistor includes a second semiconductor channel, a second gate overlapped with the second semiconductor channel, a second dielectric layer disposed between the second semiconductor channel and the second gate, and a pair of second spacers. The second dielectric layer further extends between the second gate and the pair of second spacers, the first dielectric layer is thinner than the second dielectric layer, and a width of the first gate is smaller than that of the second gate.

公开(公告)号：US10020304B2

公开(公告)日：2018-07-10

申请号：US14941673

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/16 ,  H01L27/12 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

公开(公告)号：US20180122802A1

公开(公告)日：2018-05-03

申请号：US15844639

申请日：2017-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Methods for fabricating Fin field effect transistors (FinFETs) are disclosed. First and second semiconductor fins and an insulator therebetween are formed. First and second dummy gates and an opening therebetween over the insulator are formed, wherein the first and second dummy gates cross over the first and second semiconductor fins respectively. A first dielectric material with an air gap therein is formed in the opening. A portion of the first dielectric material is removed to expose the air gap, so as to form a first dielectric layer with a slit therein. The first and second dummy gates are removed. A second dielectric layer is formed to fill the slit. First and second gates are formed to cross over portions of the first and second semiconductor fins respectively, wherein the first and second gates are electrically insulated from each other by the first dielectric layer including the second dielectric layer.

公开(公告)号：US09934985B2

公开(公告)日：2018-04-03

申请号：US14954380

申请日：2015-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/32155 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/66545

Abstract: In a method for manufacturing a semiconductor device, a dummy gate layer and a hard mask layer are sequentially formed on a substrate. A first doped portion is formed in the dummy gate layer, and has an etching selectivity with respect to the other portion of the dummy gate layer. Etching masks are formed on portions of the hard mask layer. The hard mask layer and the dummy gate layer are etched to pattern the first doped portion and the other portion of the dummy gate layer into first dummy gates and second dummy gates. The first dummy gates and the second dummy gates have different widths. A dielectric layer is formed to peripherally enclose each of the first dummy gates and each of the second dummy gates. The first dummy gates and the second dummy gates are replaced with first metal gates and second metal gates.

公开(公告)号：US09922816B2

公开(公告)日：2018-03-20

申请号：US15417115

申请日：2017-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L21/02068 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET includes a fin structure on a substrate; a dielectric layer provided on the fin structure; a metal gate crossing over the dielectric layer; two spacers respectively crossing over the dielectric layer abutting two opposite sidewalls of the metal gate, each of the two spacers having a length along a direction parallel to a longitudinal axis of the fin structure; and a source and a drain. Each of the source and the drain having a first portion peripherally enclosed by the dielectric layer, and a second portion peripherally enclosed by the two spacers, in which the length of each of the two spacers is greater than a length of the second portion, and a length of a combination of the first portion and the second portion is greater than the length of each of the two spacers.

公开(公告)号：US09899320B2

公开(公告)日：2018-02-20

申请号：US15071213

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/53295 ,  H01L29/0649 ,  H01L2221/1031

Abstract: An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second conductive layer, an insulation layer, and a plurality of air gaps. The first conductive layer is disposed over a semiconductor substrate. The dielectric layer is disposed over the first conductive layer. The second conductive layer penetrates through the dielectric layer to electrically connect with the first conductive layer. The insulation layer is located between a portion of the dielectric layer and the second conductive layer, and a material of the insulation layer and a material of the dielectric layer are different. The air gaps are located between another portion of the dielectric layer and the second conductive layer.

公开(公告)号：US09893184B2

公开(公告)日：2018-02-13

申请号：US14968920

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L21/768

CPC classification number: H01L29/7848 ,  H01L21/7684 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: In accordance with some embodiments of the present disclosure, a fin-FET device includes a substrate, a stack structure, a source and drain region, a sidewall insulator and a metal connector. The stack structure including a gate stack is disposed on the substrate. The source and drain region is disposed beside the stack structure. The sidewall insulator is disposed on the source and drain region. The sidewall insulator includes a bottom portion and an upper portion. An interface is formed between the bottom portion and the upper portion and the bottom portion is located between the upper portion and the source and drain region. The metal connector stacks on the source and drain region and the sidewall insulator is located between the metal connector and the stack structure.

公开(公告)号：US20180026033A1

公开(公告)日：2018-01-25

申请号：US15706760

申请日：2017-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin are formed. A first dummy gate, a second dummy gate and an opening between the first and second dummy gates are formed over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively. A dielectric layer is formed in the opening, wherein the dielectric layer comprises an air gap therein. The first dummy gate and the second dummy gate are replaced with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.