公开(公告)号：US12261055B2

公开(公告)日：2025-03-25

申请号：US17982028

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Chun-Hung Liao ,  Chen-Hao Wu ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

公开(公告)号：US12250824B2

公开(公告)日：2025-03-11

申请号：US18511461

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H10B51/10 ,  H10B51/20 ,  H10B53/00 ,  H10B53/10 ,  H10B53/20

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

公开(公告)号：US12002885B2

公开(公告)日：2024-06-04

申请号：US17470548

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Sheng-Tsung Wang ,  Huang-Lin Chao

IPC: H01L29/78 ,  B82Y10/00 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/481 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.

公开(公告)号：US11525072B2

公开(公告)日：2022-12-13

申请号：US17175986

申请日：2021-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Shen-Nan Lee ,  Chen-Hao Wu ,  Chun-Hung Liao ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: C09G1/02 ,  H01L21/321 ,  H01L21/762

Abstract: A chemical mechanical polishing (CMP) slurry composition includes an oxidant including oxygen, and an abrasive particle having a core structure encapsulated by a shell structure. The core structure includes a first compound and the shell structure includes a second compound different from the first compound, where a diameter of the core structure is greater than a thickness of the shell structure, and where the first compound is configured to react with the oxidant to form a reactive oxygen species.

公开(公告)号：US11495471B2

公开(公告)日：2022-11-08

申请号：US16991975

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Chun-Hung Liao ,  Chen-Hao Wu ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768

Abstract: A semiconductor substrate has an exposed surface having a compositionally uniform metal, and an embedded surface having the metal and an oxide. The exposed surface is polished using a first slurry including a first abrasive and a first amine-based alkaline until the embedded surface is exposed. The embedded surface is polished using a second slurry including a second abrasive and a second amine-based alkaline. The second abrasive is different from the first abrasive. The second amine-based alkaline is different from the first amine-based alkaline. The metal and the oxide each has a first and a second removal rate in the first slurry, respectively, and a third and fourth removal rate in the second slurry, respectively. A ratio of the first removal rate to the second removal rate is greater than 30:1, and a ratio of the third removal rate to the fourth removal rate is about 1:0.5 to about 1:2.

公开(公告)号：US20220320180A1

公开(公告)日：2022-10-06

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L27/22 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US20220181467A1

公开(公告)日：2022-06-09

申请号：US17676691

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao ,  Kuo-Liang Sung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L23/28 ,  H01L21/82 ,  H01L21/56

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.

公开(公告)号：US11257923B2

公开(公告)日：2022-02-22

申请号：US16573733

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao ,  Kuo-Liang Sung

IPC: H01L21/02 ,  H01L21/82 ,  H01L21/56 ,  H01L21/28 ,  H01L21/32 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/28

Abstract: A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.

公开(公告)号：US20210249517A1

公开(公告)日：2021-08-12

申请号：US16785919

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Peng-Soon Lim ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49

Abstract: The present disclosure describes a semiconductor device that includes a substrate and a first transistor on the substrate. The first transistor includes a first gate structure and the first gate structure includes a gate dielectric layer and a first work function layer on the gate dielectric layer. The first gate structure also includes a capping layer on the first work function layer. The semiconductor device also includes a second transistor on the substrate, in which the second transistor includes a second gate structure. The second gate structure includes the gate dielectric layer and a second work function layer on the gate dielectric layer. The second gate structure also includes the first work function layer on the second work function layer and the silicon capping layer on the first work function layer.

公开(公告)号：US20210118995A1

公开(公告)日：2021-04-22

申请号：US16657017

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.