公开(公告)号：US11823958B2

公开(公告)日：2023-11-21

申请号：US17379469

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Li-Wei Yin ,  Chen-Huang Huang ,  Ming-Jhe Sie ,  Ryan Chia-Jen Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823821 ,  H01L21/3065 ,  H01L21/76829 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

公开(公告)号：US11810909B2

公开(公告)日：2023-11-07

申请号：US17218284

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06 ,  H01L21/027 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L27/0207 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L21/0276 ,  H01L21/28556 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

公开(公告)号：US11728407B2

公开(公告)日：2023-08-15

申请号：US17809055

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

公开(公告)号：US20230253479A1

公开(公告)日：2023-08-10

申请号：US18302474

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823878 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823814 ,  H01L21/76832 ,  H01L27/0924

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US20220285530A1

公开(公告)日：2022-09-08

申请号：US17752680

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US20210408266A1

公开(公告)日：2021-12-30

申请号：US16917577

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US20210242192A1

公开(公告)日：2021-08-05

申请号：US17218284

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ming-Ching Chang

IPC: H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/06

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

公开(公告)号：US20210090958A1

公开(公告)日：2021-03-25

申请号：US17114082

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Uei Jang ,  Chen-Huang Huang ,  Ryan Chia-Jen Chen ,  Shiang-Bau Wang ,  Shu-Yuan Ku

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.