公开(公告)号：US12107149B2

公开(公告)日：2024-10-01

申请号：US18302474

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US11996466B2

公开(公告)日：2024-05-28

申请号：US17739708

申请日：2022-05-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Huang Huang ,  Ming-Jhe Sie ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Shu-Uei Jang ,  An Chyi Wei ,  Shiang-Bau Wang ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

公开(公告)号：US11652155B2

公开(公告)日：2023-05-16

申请号：US17752680

申请日：2022-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092

CPC分类号： H01L29/66545 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

摘要： In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US20220209023A1

公开(公告)日：2022-06-30

申请号：US17699477

申请日：2022-03-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Chung Chang ,  Hsiu-Hao Tsao ,  Ming-Jhe Sie ,  Shun-Hui Yang ,  Chen-Huang Huang ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065

摘要： A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

公开(公告)号：US10131539B2

公开(公告)日：2018-11-20

申请号：US15725752

申请日：2017-10-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Han Meng ,  Chih-Hsien Hsu ,  Chia-Chi Chung ,  Yu-Pei Chiang ,  Wen-Chih Chen ,  Chen-Huang Huang ,  Zhi-Sheng Xu ,  Jr-Sheng Chen ,  Kuo-Chin Liu ,  Lin-Ching Huang

IPC分类号： B81C1/00 ,  H01H59/00 ,  H01G5/18 ,  B81B3/00

摘要： A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

公开(公告)号：US20240297235A1

公开(公告)日：2024-09-05

申请号：US18658521

申请日：2024-05-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Huang Huang ,  Ming-Jhe Sie ,  Yih-Ann Lin ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC分类号： H01L29/49 ,  H01L21/285 ,  H01L21/764 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4991 ,  H01L21/28518 ,  H01L21/764 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

摘要： A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.

公开(公告)号：US20240355906A1

公开(公告)日：2024-10-24

申请号：US18303989

申请日：2023-04-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shao-Hua Hsu ,  Chia-I Lin ,  Hsiu-Hao Tsao ,  Kai-Min Chien ,  Chen-Huang Huang ,  An Chyi Wei ,  Ryan Chia-Jen Chen

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/40

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66818

摘要： Embodiments include a method and device resulting from the method, including using a radical oxidation process to oxidize a spacer layer which lines the opening after removing a dummy gate electrode. The oxidized layer is removed by an etching process. An STI region disposed below the dummy gate electrode may be partially etched.

公开(公告)号：US20240290869A1

公开(公告)日：2024-08-29

申请号：US18643031

申请日：2024-04-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Huang Huang ,  Ming-Jhe Sie ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Shu-Uei Jang ,  An Chyi Wei ,  Shiang-Bau Wang ,  Ryan Chia-Jen Chen

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

公开(公告)号：US11848240B2

公开(公告)日：2023-12-19

申请号：US17114082

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shu-Uei Jang ,  Chen-Huang Huang ,  Ryan Chia-Jen Chen ,  Shiang-Bau Wang ,  Shu-Yuan Ku

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

公开(公告)号：US20210351084A1

公开(公告)日：2021-11-11

申请号：US17379469

申请日：2021-07-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shiang-Bau Wang ,  Li-Wei Yin ,  Chen-Huang Huang ,  Ming-Jhe Sie ,  Ryan Chia-Jen Chen

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

摘要： In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.