公开(公告)号：US10978362B2

公开(公告)日：2021-04-13

申请号：US16683619

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Chun Tsai ,  Wei-Sen Chang ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L21/66 ,  H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  G01R31/28 ,  G01R31/00 ,  G01R1/073 ,  G01R31/50

Abstract: A method for forming a semiconductor device structure and method for forming the same are provided. The method includes forming a conductive pad over the substrate, and forming a protection layer over the conductive pad. The method also includes forming a conductive structure accessibly arranged through the protection layer and electrically connected to the conductive pad, and the conductive structure has a curved top surface. A lowest point of the curved top surface of the conductive structure is higher than a topmost surface of the protection layer.

公开(公告)号：US20210091059A1

公开(公告)日：2021-03-25

申请号：US16951511

申请日：2020-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Kuo Lung Pan ,  Hung-Yi Kuo ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/24

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

公开(公告)号：US20200381362A1

公开(公告)日：2020-12-03

申请号：US16425957

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Cheng Tseng ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Chia-Hung Liu ,  Chi-Hui Lai

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a first wafer, a second wafer, and an interconnect. The first wafer includes a first die, a first encapsulating material encapsulating the first die, and a first redistribution structure disposed over the first die and the first encapsulating material. The second wafer includes a second die, a second encapsulating material encapsulating the second die, and a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure faces the first redistribution structure. The interconnect is disposed between the first wafer and the second wafer and electrically connecting the first redistribution structure and the second redistribution structure, wherein the interconnect includes a substrate and a plurality of through vias extending through the substrate for connecting the first redistribution structure and the second redistribution structure.

公开(公告)号：US10833033B2

公开(公告)日：2020-11-10

申请号：US16458324

申请日：2019-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.

公开(公告)号：US20200303316A1

公开(公告)日：2020-09-24

申请号：US16897299

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chang ,  Hao-Yi Tsai ,  Tsung-Hsien Chiang ,  Tin-Hao Kuo

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes a redistribution layer (RDL) structure, a die, and an encapsulant. The die is attached to the RDL structure through an adhesive layer. The encapsulant is disposed on the RDL structure and laterally encapsulates the die and the adhesive layer. The encapsulant includes a protruding part extending into the RDL structure and having a bottom surface in contact with the RDL structure.

公开(公告)号：US20200294916A1

公开(公告)日：2020-09-17

申请号：US16354105

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies.

公开(公告)号：US20200243483A1

公开(公告)日：2020-07-30

申请号：US16258677

申请日：2019-01-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tin-Hao Kuo ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Yu-Chia Lai ,  Po-Yuan Teng

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H05K1/02 ,  H01L25/00

Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.

公开(公告)号：US10658258B1

公开(公告)日：2020-05-19

申请号：US16281094

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Lung Pan ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/29 ,  H01L23/48 ,  H01L23/15 ,  H01L23/28 ,  H01L23/522 ,  H01L23/14 ,  H01L23/528

Abstract: A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

公开(公告)号：US20200135692A1

公开(公告)日：2020-04-30

申请号：US16713009

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Chen ,  Chih-Hua Chen ,  Hsin-Yu Pan ,  Hao-Yi Tsai ,  Lipu Kris Chuang ,  Tin-Hao Kuo

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/373 ,  H01L23/367

Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

公开(公告)号：US10510686B2

公开(公告)日：2019-12-17

申请号：US15964087

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Ching-Yao Lin ,  Teng-Yuan Lo ,  Chih Wang

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L25/11

Abstract: A semiconductor package and a manufacturing method thereof are provided with the following steps, attaching a rear surface of a semiconductor die on a first redistribution structure by a die attach material, wherein the semiconductor die is pressed so that the die attach material is extruded laterally out and climbs upwardly to cover a sidewall of the semiconductor die, and after attaching, the die attach material comprises an extruded region surrounding the semiconductor die, a first shortest distance from a midpoint of an bottom edge of semiconductor die to a midpoint of an bottom edge of extruded region in a width direction is greater than a second shortest distance between an endpoint of the bottom edge of semiconductor die to an endpoint of the bottom edge of extruded region; and forming an insulating encapsulant on the first redistribution structure to encapsulate the semiconductor die and the die attach material.