公开(公告)号：US20190326240A1

公开(公告)日：2019-10-24

申请号：US16458324

申请日：2019-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.

公开(公告)号：US10163801B2

公开(公告)日：2018-12-25

申请号：US15293577

申请日：2016-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo

IPC: H01L33/48 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer arranged over the semiconductor die and the protection layer and partially covering the conductive feature. The conductive feature is arranged accessibly from the protection layer and the dielectric layer. The chip package further includes a conductive layer penetrating through the dielectric layer and electrically connected to the conductive feature of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion accessibly exposed from the dielectric layer, and the second portion has a surface roughness greater than that of the first portion.

公开(公告)号：US20210050281A1

公开(公告)日：2021-02-18

申请号：US17073937

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Horng Chang ,  Jie-Cheng Deng ,  Tin-Hao Kuo ,  Ying-Yu Chen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

公开(公告)号：US20210035938A1

公开(公告)日：2021-02-04

申请号：US17075904

申请日：2020-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

公开(公告)号：US20160181223A1

公开(公告)日：2016-06-23

申请号：US15057302

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece. The conductive bump has a recess. A reflow process is performed on a solder layer to electrically couple the conductive trace and the conductive bump. The solder layer fills a part of the recess during the reflow process. By filling the recess during the reflow process, electrical shorting between the conductive trace and an adjacent conductive is reduced.

Abstract translation: 在一些实施例中，本发明涉及集成芯片接合的方法。 该方法在第一工件的表面上形成导电迹线，并在第二工件的表面上形成导电凸块。 导电凸块具有凹部。 在焊料层上进行回流处理，以电耦合导电迹线和导电凸块。 在回流过程中，焊料层填充凹部的一部分。 通过在回流工艺期间填充凹槽，导电迹线和相邻导电体之间的电短路减小。

公开(公告)号：US12100682B2

公开(公告)日：2024-09-24

申请号：US16035696

申请日：2018-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chih-Horng Chang ,  Hao-Yi Tsai ,  Chih-Hsuan Tai

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L24/20 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/19 ,  H01L24/25 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/24145 ,  H01L2224/2518 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19102 ,  H01L2924/2064

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a redistribution circuit structure. The semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure includes conductive patterns, wherein the conductive patterns each comprise a first portion, at least one second portion, and at least one connecting portion. A first edge of the at least one connecting portion is connected to the first portion, and a second edge of the at least one connecting portion is connected to the at least one second portion, wherein the first edge is opposite to the second edge, and a length of the first edge is greater than a length of the second edge.

公开(公告)号：US11631648B2

公开(公告)日：2023-04-18

申请号：US17075904

申请日：2020-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

Abstract: The present disclosure relates to an integrated chip structure having a first copper pillar disposed over a metal pad of an interposer substrate. The first copper pillar has a sidewall defining a recess. A nickel layer is disposed over the first copper pillar and a solder layer is disposed over the first copper pillar and the nickel layer. The solder layer continuously extends from directly over the first copper pillar to within the recess. A second copper layer is disposed between the solder layer and a second substrate.

公开(公告)号：US10388622B2

公开(公告)日：2019-08-20

申请号：US15803008

申请日：2017-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.

公开(公告)号：US09520379B2

公开(公告)日：2016-12-13

申请号：US15057302

申请日：2016-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece. The conductive bump has a recess. A reflow process is performed on a solder layer to electrically couple the conductive trace and the conductive bump. The solder layer fills a part of the recess during the reflow process. By filling the recess during the reflow process, electrical shorting between the conductive trace and an adjacent conductive is reduced.

Abstract translation: 在一些实施例中，本发明涉及集成芯片接合的方法。 该方法在第一工件的表面上形成导电迹线，并在第二工件的表面上形成导电凸块。 导电凸块具有凹部。 在焊料层上进行回流处理，以电耦合导电迹线和导电凸块。 在回流过程中，焊料层填充凹部的一部分。 通过在回流工艺期间填充凹槽，导电迹线和相邻导电体之间的电短路减小。

公开(公告)号：US11776880B2

公开(公告)日：2023-10-03

申请号：US17073937

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Jie-Cheng Deng ,  Tin-Hao Kuo ,  Ying-Yu Chen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/48 ,  H01L21/563 ,  H01L23/3142 ,  H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/92125 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.