公开(公告)号：US11495503B2

公开(公告)日：2022-11-08

申请号：US17373303

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

公开(公告)号：US11349009B2

公开(公告)日：2022-05-31

申请号：US16901340

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Yu-Kuan Lin

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L27/11

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yttrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

公开(公告)号：US11296095B2

公开(公告)日：2022-04-05

申请号：US16900200

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/786

Abstract: A memory device includes a substrate, first semiconductor layers and second semiconductor layers alternately stacked over the substrate, a first gate structure and a second gate structure crossing the first semiconductor layers and the second semiconductor layers, a first via and a second via over the first gate structure and the second gate structure, and a first word line and a second word line over the first via and the second via. Along a lengthwise direction of the first and second gate structures, a width of the first semiconductor layers is narrower than a width of the second semiconductor layers.

公开(公告)号：US20210343601A1

公开(公告)日：2021-11-04

申请号：US17373303

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

公开(公告)号：US11133230B2

公开(公告)日：2021-09-28

申请号：US16801576

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate having a first region and a second region; a first semiconductor fin formed on the substrate within the first region; a second semiconductor fin formed on the substrate within the second region; a first liner layer disposed along a lower portion of the first semiconductor fin and a lower portion of the second semiconductor fin; a second liner layer disposed over the first liner layer in the second region, wherein the second liner layer is different from the first liner layer in composition; and an isolation feature disposed on the first liner layer in the first region and on the second liner layer in the second region, and separating lower portions of the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US11062963B2

公开(公告)日：2021-07-13

申请号：US16521870

申请日：2019-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  H01L27/11 ,  H01L21/762 ,  G06F30/392

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.

公开(公告)号：US10050045B1

公开(公告)日：2018-08-14

申请号：US15625490

申请日：2017-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hsiu Hsu ,  Yu-Kuan Lin ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/419

Abstract: An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

公开(公告)号：US20180138185A1

公开(公告)日：2018-05-17

申请号：US15354052

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/1052 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66803

Abstract: A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate. The second transistor is disposed on the substrate. A gate of the first transistor and a gate of the second transistor are integrally formed, and the first transistor and the second transistor have different threshold voltages.

公开(公告)号：US12027202B2

公开(公告)日：2024-07-02

申请号：US17877049

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Wei Wang ,  Chia-Hao Pao ,  Choh Fei Yeap ,  Yu-Kuan Lin ,  Kian-Long Lim

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H10B10/12

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

公开(公告)号：US20230369496A1

公开(公告)日：2023-11-16

申请号：US18359034

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/76224 ,  H01L21/02579 ,  H01L21/02576 ,  H01L21/02532

Abstract: A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.