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公开(公告)号:US20220359686A1
公开(公告)日:2022-11-10
申请号:US17815089
申请日:2022-07-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Li-Zhen Yu , Lin-Yu Huang , Cheng-Chi Chuang , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L29/417 , H01L29/49 , H01L29/78 , H01L29/66 , H01L21/285 , H01L21/321 , H01L21/8234 , H01L23/528 , H01L23/535
Abstract: A semiconductor structure includes a metal gate structure (MG) formed over a substrate, a first gate spacer formed on a first sidewall of the MG, a second gate spacer formed on a second sidewall of the MG opposite to the first sidewall, where the second gate spacer is shorter than the first gate spacer, a source/drain (S/D) contact (MD) adjacent to the MG, where a sidewall of the MD is defined by the second gate spacer, and a contact feature configured to electrically connect the MG to the MD.
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公开(公告)号:US20220358983A1
公开(公告)日:2022-11-10
申请号:US17814755
申请日:2022-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chenchen Wang , Sai-Hooi Yeong , Chi On Chui , Yu-Ming Lin
Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.
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公开(公告)号:US20220352380A1
公开(公告)日:2022-11-03
申请号:US17811212
申请日:2022-07-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Hao Chang , Lin-Yu Huang , Han-Jong Chia , Bo-Feng Young , Yu-Ming Lin
Abstract: A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.
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公开(公告)号:US20220285349A1
公开(公告)日:2022-09-08
申请号:US17747694
申请日:2022-05-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Meng-Han Lin , Han-Jong Chia , Sai-Hooi Yeong , Chi On Chui , Yu-Ming Lin
IPC: H01L27/108 , H01L49/02 , H01L29/423
Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.
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公开(公告)号:US11411011B2
公开(公告)日:2022-08-09
申请号:US17132305
申请日:2020-12-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chao-I Wu , Yu-Ming Lin , Han-Jong Chia
IPC: H01L27/11502 , H01L27/11585 , G11C11/22 , G11C5/06
Abstract: A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.
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公开(公告)号:US20220238693A1
公开(公告)日:2022-07-28
申请号:US17717684
申请日:2022-04-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Cheng-Chi Chuang , Lin-Yu Huang , Chia-Hao Chang , Yu-Ming Lin , Ting-Ya Lo , Chi-Lin Teng , Hsin-Yen Huang , Hai-Ching Chen
IPC: H01L29/66 , H01L29/49 , H01L29/78 , H01L21/8234
Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.
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公开(公告)号:US11373910B2
公开(公告)日:2022-06-28
申请号:US16897229
申请日:2020-06-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yasutoshi Okuno , Cheng-Yi Peng , Ziwei Fang , I-Ming Chang , Akira Mineji , Yu-Ming Lin , Meng-Hsuan Hsiao
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/203 , H01L27/092 , H01L21/8238 , H01L29/165 , H01L27/12 , H01L21/84 , H01L29/161
Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0
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公开(公告)号:US20220130823A1
公开(公告)日:2022-04-28
申请号:US17572212
申请日:2022-01-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Huan-Chieh Su , Li-Zhen Yu , Chun-Yuan Chen , Shih-Chuan Chiu , Cheng-Chi Chuang , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L27/088 , H01L21/027 , H01L21/308 , H01L21/306
Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
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公开(公告)号:US11264284B2
公开(公告)日:2022-03-01
申请号:US16690092
申请日:2019-11-20
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jia-Chuan You , Chia-Hao Chang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
IPC: H01L21/8234 , H01L29/78 , H01L29/417 , H01L29/66
Abstract: A semiconductor device includes a semiconductor substrate, a gate stack, an air spacer, a first spacer, a second spacer, a sacrificial layer, and a contact plug. The gate stack is on the semiconductor substrate. The air spacer is around the gate stack. The first spacer is around the air spacer. The second spacer is on the air spacer and the first spacer. The sacrificial layer is on the gate stack, and an etching selectivity between the second spacer and the sacrificial layer is in a range from about 10 to about 30. The contact plug lands on the second spacer and the gate stack.
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公开(公告)号:US11251087B2
公开(公告)日:2022-02-15
申请号:US16897234
申请日:2020-06-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yasutoshi Okuno , Cheng-Yi Peng , Ziwei Fang , I-Ming Chang , Akira Mineji , Yu-Ming Lin , Meng-Hsuan Hsiao
IPC: H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/203 , H01L27/092 , H01L21/8238 , H01L29/165 , H01L27/12 , H01L21/84 , H01L29/161
Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1−x−yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01≤x≤0.1, and 0.01≤y≤0.1.
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