公开(公告)号：US08748266B2

公开(公告)日：2014-06-10

申请号：US13291999

申请日：2011-11-08

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20100173461A1

公开(公告)日：2010-07-08

申请号：US12724323

申请日：2010-03-15

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20070217741A1

公开(公告)日：2007-09-20

申请号：US11803249

申请日：2007-05-14

申请人： Takashi Shigenaga ,  Katsuki Suematsu ,  Hiroshi Matsuura ,  Renichi Yuguchi ,  Takashi Shigematsu

发明人： Takashi Shigenaga ,  Katsuki Suematsu ,  Hiroshi Matsuura ,  Renichi Yuguchi ,  Takashi Shigematsu

IPC分类号： G02B6/32

CPC分类号： G02B6/32 ,  G02B6/322 ,  G02B6/327 ,  G02B6/3885

摘要： An optical module including first and second lens housings that individually receive first and second lenses; first and second optical fiber housings that individually receive end portions of optical fibers; first and second guide pins for positioning the first and second lens housings and the first and second optical fiber housings, with the first and second lens housings abutted against each other at their inner end faces and disposed between the first and second optical fiber units so as to be abutted thereto; two first positioning members provided between the first optical fiber housing and the first lens and between the second optical fiber housing and the second lens, respectively; and a second positioning member disposed between the first and second lenses.

摘要翻译： 一种光学模块，包括单独接收第一和第二透镜的第一和第二透镜壳体; 分别容纳光纤端部的第一和第二光纤壳体; 用于定位第一和第二透镜壳体以及第一和第二光纤壳体的第一和第二引导销，其中第一和第二透镜壳体在其内端面处彼此抵靠并设置在第一和第二光纤单元之间，以便 邻接; 分别设置在第一光纤壳体和第一透镜之间以及第二光纤壳体和第二透镜之间的两个第一定位部件; 以及设置在第一和第二透镜之间的第二定位构件。

公开(公告)号：US20050037579A1

公开(公告)日：2005-02-17

申请号：US10948262

申请日：2004-09-24

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US06803281B2

公开(公告)日：2004-10-12

申请号：US10785103

申请日：2004-02-25

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US06720220B2

公开(公告)日：2004-04-13

申请号：US10325915

申请日：2002-12-23

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US08076202B2

公开(公告)日：2011-12-13

申请号：US12724323

申请日：2010-03-15

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20070290239A1

公开(公告)日：2007-12-20

申请号：US11878846

申请日：2007-07-27

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L29/76

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US07180130B2

公开(公告)日：2007-02-20

申请号：US10948262

申请日：2004-09-24

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L29/792

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US06947636B2

公开(公告)日：2005-09-20

申请号：US10147283

申请日：2002-05-14

申请人： Atsushi Shinozaki ,  Takashi Shigematsu ,  Toshihiko Ota ,  Shigehito Yodo

发明人： Atsushi Shinozaki ,  Takashi Shigematsu ,  Toshihiko Ota ,  Shigehito Yodo

IPC分类号： G02B6/00 ,  G02B6/02 ,  G02B6/34

CPC分类号： G02B6/0218 ,  G02B6/022

摘要： An optical module comprises an optical fiber having a formed portion to form a fiber grating and a package to which the optical fiber is secured. The package comprises a single package member or at least two or more package members whose materials differ from each other. The optical fiber is secured to the package member. A distortion for adjusting a Bragg reflection wavelength of the fiber grating of the optical fiber is given to the package member.

摘要翻译： 光学模块包括具有形成部分以形成光纤光栅的光纤和光纤固定到其上的封装。 该包装包括单个包装件或至少两个或更多个包装件，其材料彼此不同。 光纤固定在封装件上。 向包装件施加用于调节光纤的光纤光栅的布拉格反射波长的失真。