公开(公告)号：US20060014081A1

公开(公告)日：2006-01-19

申请号：US11129403

申请日：2005-05-16

申请人： Rumiko Hayase ,  Akiko Hirao ,  Kazuki Matsumoto ,  Takayuki Tsukamoto ,  Katsutaro Ichihara ,  Urara Ichihara

发明人： Rumiko Hayase ,  Akiko Hirao ,  Kazuki Matsumoto ,  Takayuki Tsukamoto ,  Katsutaro Ichihara ,  Urara Ichihara

IPC分类号： G03H1/02 ,  G03C1/735

CPC分类号： G11B7/0065 ,  G03H2001/026 ,  G03H2001/0264 ,  G11B7/245 ,  G11B7/26

摘要： Disclosed is a holographic recording medium and methods of manufacturing the holographic recording medium. The example of the medium has a recording layer containing a three dimensionally cross-linked polymer matrix including an epoxy resin, a radically polymerizable monomer, and a photo radical polymerization initiator. The radically polymerizable monomer comprises both N-vinylcarbazole (VC) and N-vinylpyrrolidone (VP) or N-vinylcarbazole alone. The weight ratio of N-vinylcarbazole (VC) to the sum of N-vinylcarbazole (VC) and N-vinylpyrrolidone (VP), i.e., (VC/(VC+VP)), is not smaller than 0.75 and not larger than 1.0.

公开(公告)号：US09099180B2

公开(公告)日：2015-08-04

申请号：US13599301

申请日：2012-08-30

申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Tomonori Kurosawa ,  Mizuki Kaneko

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

摘要： According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

摘要翻译： 根据一个实施例，半导体存储器件包括多个单元阵列块和控制电路。 控制电路将所选择的位线设置为具有0伏特，对所选择的字线施加高于0伏的第一电位，将比第一电位高于0伏且低于第一电位的第二电位施加到非 - 除了所选字线以外的选定字线，将相邻单元阵列块中与选定位线相邻的未选位线施加0伏以上且低于第2电位的第3电位， 对除了施加了第三电位的未选位线之外的非选择位线的第二电位，并且改变所选存储单元的电阻变化膜的电阻状态。

公开(公告)号：US08837199B2

公开(公告)日：2014-09-16

申请号：US13599265

申请日：2012-08-30

申请人： Hiroshi Kanno ,  Yoichi Minemura ,  Mizuki Kaneko ,  Tomonori Kurosawa ,  Takafumi Shimotori ,  Takayuki Tsukamoto

发明人： Hiroshi Kanno ,  Yoichi Minemura ,  Mizuki Kaneko ,  Tomonori Kurosawa ,  Takafumi Shimotori ,  Takayuki Tsukamoto

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of memory cells, a plurality of wires, and a control circuit. The control circuit allows a first current to change a state to flow on a selected cell by applying a first potential difference between a pair of wires that sandwich the selected cell selected from the plurality of memory cells with respect to the semiconductor substrate vertically, and allows a second current lower than the first current to flow on an non-selected cell in the same direction as the direction of the first current by applying a second potential difference between a pair of wires that sandwich the non-selected cell connected to a wire shared with the selected cell on a different layer from the selected cell.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，多个存储单元，多根导线和控制电路。 控制电路允许第一电流通过在相对于半导体衬底垂直地夹持从多个存储单元中选择的所选择的单元的一对导线之间施加第一电位差来改变选定单元上的状态，并允许 低于第一电流的第二电流，在与所述第一电流的方向相同的方向上在未选择的单元上流动，通过在连接到共享的线的未选择的单元之间施加一对导线之间的第二电位差 所选单元格与选定单元格不同的图层。

公开(公告)号：US08488367B2

公开(公告)日：2013-07-16

申请号：US13052174

申请日：2011-03-21

申请人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

发明人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/005 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72

摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.

摘要翻译： 根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到 存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。 如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。

公开(公告)号：US08487345B2

公开(公告)日：2013-07-16

申请号：US12885952

申请日：2010-09-20

申请人： Takayuki Tsukamoto ,  Tsukasa Nakai ,  Akira Kikitsu ,  Takeshi Yamaguchi ,  Sumio Ashida

发明人： Takayuki Tsukamoto ,  Tsukasa Nakai ,  Akira Kikitsu ,  Takeshi Yamaguchi ,  Sumio Ashida

IPC分类号： H01L21/02

CPC分类号： G11B11/002 ,  B82Y10/00 ,  G11B9/04 ,  G11B9/149 ,  G11B11/08 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C16/0483 ,  G11C2211/565 ,  G11C2213/53 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

摘要： According to one embodiment, an information recording and reproducing device includes a stacked body. The stacked body includes a first layer, a second layer and a recording layer provided between the first layer and the second layer. The recording layer includes a phase-change material and a crystal nucleus. The phase-change material is capable of reversely changing between a crystal state and an amorphous state by a current supplied via the first layer and the second layer. The crystal nucleus is provided in contact with the phase-change material and includes a crystal nucleus material having a crystal structure identical to a crystal structure of the crystal state of the phase-change material, and a crystal nucleus coating provided on a surface of the crystal nucleus material and having a composition different from a composition of the crystal nucleus material.

摘要翻译： 根据一个实施例，信息记录和再现装置包括堆叠体。 层叠体包括设置在第一层和第二层之间的第一层，第二层和记录层。 记录层包括相变材料和晶核。 相变材料能够通过经由第一层和第二层提供的电流在晶体状态和非晶状态之间反向变化。 提供与相变材料接触的晶核，并且包括具有与相变材料的晶体状态的晶体结构相同的晶体结构的晶核材料，以及设置在相变材料的表面上的晶核涂层 并且具有与晶核材料的组成不同的组成的晶核材料。

公开(公告)号：US08274815B2

公开(公告)日：2012-09-25

申请号：US12886931

申请日：2010-09-21

申请人： Reika Ichihara ,  Takayuki Tsukamoto

发明人： Reika Ichihara ,  Takayuki Tsukamoto

IPC分类号： G11C11/00

CPC分类号： G11C11/00 ,  G11C2013/0083

摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

摘要翻译： 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

公开(公告)号：US20120134444A1

公开(公告)日：2012-05-31

申请号：US13298897

申请日：2011-11-17

申请人： Takayuki Tsukamoto

发明人： Takayuki Tsukamoto

IPC分类号： H03D1/24

CPC分类号： H04L27/06 ,  G06K7/0008 ,  H03D1/00 ,  H04B5/0031

摘要： A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration.

摘要翻译： 当NFC功能半导体器件以除R / W模式之外的模式工作时，器件通过使用与用于R / W模式的ASK信号接收电路不同的ASK信号接收电路来接收ASK信号。 在一对发送端子的一侧设置有用于100％ASK的ASK信号接收电路。 这种布置消除了在与一对接收终端耦合的10％ASK的ASK信号接收电路内提供的ESD的影响。 不需要根据ASK的类型来管理不同的阈值，并且可以通过较小的电路配置来支持不同的调制方案。

公开(公告)号：US20110235400A1

公开(公告)日：2011-09-29

申请号：US13052174

申请日：2011-03-21

申请人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

发明人： Takafumi Shimotori ,  Yoichi Minemura ,  Hiroshi Kanno ,  Takayuki Tsukamoto ,  Jun Nishimura ,  Masahiro Une

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/005 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2213/72

摘要： According to one embodiment, a method for controlling a semiconductor device comprises determining a select bit number for a group of memory cells each includes a variable-resistance element, setting a first voltage corresponding to the select bit number, applying the set first voltage to the memory cell group, and performing verify read on the memory cell group to which the first voltage has been applied and determining whether or not the memory cell group passes the verify read. If the memory cell group is determined not to pass the verify read, the number of bits corresponding to passed memory cells is subtracted from the select bit number, and the first voltage corresponding to the decreased select bit number is set again.

摘要翻译： 根据一个实施例，一种用于控制半导体器件的方法包括确定一组存储器单元的选择位数，每个存储单元包括可变电阻元件，设置与选择位数对应的第一电压，将所设置的第一电压施加到 存储单元组，并对已经施加了第一电压的存储单元组执行验证读取，并确定存储单元组是否通过验证读取。 如果确定存储单元组不通过验证读取，则从选择位数中减去与传递的存储器单元相对应的位数，并且再次设置与减小的选择位数相对应的第一电压。

公开(公告)号：US20110037044A1

公开(公告)日：2011-02-17

申请号：US12921471

申请日：2009-03-10

申请人： Takeshi Araki ,  Takayuki Tsukamoto ,  Takeshi Yamaguchi

发明人： Takeshi Araki ,  Takayuki Tsukamoto ,  Takeshi Yamaguchi

IPC分类号： H01L45/00

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： This disclosure provides an information recording device for use in a non-volatile information recording/reproduction system having a high recording density, the device including a resistive material having less phase separation or the like during switching. This disclosure also provides an information recording/reproduction system including the device. This disclosure provides an information recording device including: a pair of electrodes; and a recording layer between the electrodes, the recording layer recording information by its resistance change, the recording layer including at least one of (a) M3Oz and (b) AxM3—x0z as a main component, in (a) and (b), z being a value representing oxygen deficiency from z=4.5, and in (b), x satisfying 0.00

摘要翻译： 本公开提供了一种用于具有高记录密度的非易失性信息记录/再现系统中的信息记录装置，该装置包括在切换期间具有较小相位分离等的电阻材料。 本公开还提供了包括该设备的信息记录/再现系统。 本公开提供一种信息记录装置，包括：一对电极; （a）和（b）中的（a）M3Oz和（b）AxM3-x0z中的至少一个作为主要成分，记录层通过其电阻变化记录信息，记录层记录信息， z表示从z = 4.5表示氧缺乏的值，在（b）中，x满足0.00

公开(公告)号：US20110026299A1

公开(公告)日：2011-02-03

申请号：US12713667

申请日：2010-02-26

申请人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka

发明人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C5/025 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

摘要： A nonvolatile semiconductor memory device comprises: a plurality of first lines; a plurality of second lines; a plurality of memory cells each disposed at each of crossing-points of the first lines and the second lines and each comprising a variable resistor and a bi-directional diode; and a voltage control circuit configured to control a voltage of selected one of the first lines, unselected ones of the first lines, selected one of the second lines, and unselected ones of the second lines, respectively. The variable resistor is configured to change its resistance value depending on a polarity of a voltage applied thereto. The voltage control circuit is configured to apply a voltage pulse to the selected one of the first lines and to connect a capacitor of a certain capacitance to one end of the selected one of the second lines.

摘要翻译： 非易失性半导体存储器件包括：多条第一线; 多条第二线; 多个存储单元，每个存储单元分别设置在第一线和第二线的交叉点的每一个处，并且每个存储单元包括可变电阻器和双向二极管; 以及电压控制电路，被配置为分别控制所选择的第一行，未选择的第一行，所选择的第二行和未选择的第二行中的一个的电压。 可变电阻器被配置为根据施加到其的电压的极性来改变其电阻值。 电压控制电路被配置为向所选择的第一线中的一个施加电压脉冲，并且将一定电容的电容器连接到所选择的一条第二线路的一端。