公开(公告)号：US20120185812A1

公开(公告)日：2012-07-19

申请号：US13005599

申请日：2011-01-13

申请人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

发明人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.

摘要翻译： 一种用于开发集成电路内的子电路的精简网表的系统和方法，以及基于精简网表而不是完整的网表来对集成电路的性能进行建模。 IC布局被分割成多个子电路，每个子电路包括通过类似的电阻网络连接到（即共享）相同的电子电路终端的给定类型的有源设备中的一个或多个的组 它们受到大致相同的总体组合寄生电阻）。 从布局中提取与子电路对应的完整网表，并进行浓缩。 每个浓缩网表列出了子电路中的有源器件和电阻网络所呈现的性能变化（例如，作为工作电源电压，工作温度以及任选的自发热和/或应力的变化的函数）。 然后在集成电路的工作温度和工作电源电压的全范围内模拟子电路的精简网表，以便为集成电路生成性能模型。

公开(公告)号：US20110263101A1

公开(公告)日：2011-10-27

申请号：US13170525

申请日：2011-06-28

申请人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L21/20 ,  B82Y40/00

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过电介质层对两个器件区域之间的电介质层进行电偏置 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

公开(公告)号：US08037433B2

公开(公告)日：2011-10-11

申请号：US12196471

申请日：2008-08-22

申请人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

发明人： Dureseti Chidambarrao ,  Tong Li ,  Richard Q. Williams ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.

摘要翻译： 分析半导体电路的布局以计算可以包括迁移率偏移和阈值电压偏移的依赖于布局的参数。 影响依赖于布局的参数的依赖于布局的效应可能包括应力影响，快速热退火（RTA）效应和平版印刷效应。 计算不反映与布局有关的影响的内在函数，然后根据与布局相关的参数计算缩放修正符号。 通过将每个内在函数与相应的缩放参数相乘来获得反映与布局相关的效应的模型输出函数。

公开(公告)号：US20100295025A1

公开(公告)日：2010-11-25

申请号：US12850259

申请日：2010-08-04

申请人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

公开(公告)号：US07659579B2

公开(公告)日：2010-02-09

申请号：US11539288

申请日：2006-10-06

申请人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L29/78

CPC分类号： H01L29/78612 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78648

摘要： A FET has a shallow source/drain region, a deep channel region, a gate stack and a back gate that is surrounded by dielectric. The FET structure also includes halo or pocket implants that extend through the entire depth of the channel region. Because a portion of the halo and well doping of the channel is deeper than the source/drain depth, better threshold voltage and process control is achieved. A back-gated FET structure is also provided having a first dielectric layer in this structure that runs under the shallow source/drain region between the channel region and the back gate. This first dielectric layer extends from under the source/drain regions on either side of the back gate and is in contact with a second dielectric such that the back gate is bounded on each side or isolated by dielectric.

摘要翻译： FET具有浅电源/漏极区域，深沟道区域，栅极堆叠和被电介质包围的背栅极。 FET结构还包括延伸通过通道区域的整个深度的晕或凹坑植入物。 因为沟道的一部分光晕和阱掺杂比源极/漏极深度更深，所以实现了更好的阈值电压和过程控制。 还提供了后栅化FET结构，其具有在该结构中的第一介电层，其在沟道区域和后栅极之间的浅源极/漏极区域下方延伸。 该第一电介质层从背栅的两侧的源极/漏极区下方延伸并与第二电介质接触，使得后栅极在每一侧上界定或通过电介质隔离。

公开(公告)号：US07627840B2

公开(公告)日：2009-12-01

申请号：US11457174

申请日：2006-07-13

申请人： A J Kleinosowski ,  Philip J. Oldiges ,  Paul M. Solomon ,  Richard Q. Williams

发明人： A J Kleinosowski ,  Philip J. Oldiges ,  Paul M. Solomon ,  Richard Q. Williams

IPC分类号： G06F17/50 ,  H01L29/94

CPC分类号： G06F17/5036 ,  G01R31/31816 ,  G01R31/318357

摘要： A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.

摘要翻译： 在逻辑电路中对软错误进行建模的方法使用在设备的源极和漏极处插入的两个单独的电流源来模拟由例如α粒子撞击引起的单个事件不正常（SEU）。 在nfet实现中，电流从源极或漏极流向器件的主体。 具有已知幅度的电流波形在电流源处被注入，同时模拟逻辑电路的操作，并且根据模拟操作确定逻辑电路的状态。 可以独立调整电流波形的幅度。 模拟器监视设备的状态，并在转换发生时创建日志条目。 逻辑电路中的其他器件可以重复该过程，以提供电路对软错误的敏感性的整体表征。

公开(公告)号：US07579655B2

公开(公告)日：2009-08-25

申请号：US11275475

申请日：2006-01-09

申请人： Hussein I. Hanafi ,  Richard Q. Williams

发明人： Hussein I. Hanafi ,  Richard Q. Williams

IPC分类号： H01L29/76

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66772

摘要： A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical contact with the interconnect. The low-resistivity local interconnect is advantageous for use with stressed liner films since a conductor can contact the interconnect at a distance from the diffusion, thus allowing electrical contact without having to interrupt the stress liner film where it is most effective. Several embodiments of methods of electrically connecting a diffusion to an interconnect are also disclosed.

摘要翻译： 公开了一种晶体管结构，其包括至少一个晶体管，其包括扩散和电连接到扩散侧的互连和与互连电接触的导体。 低电阻率局部互连有利于与应力衬垫膜一起使用，因为导体可以在距离扩散一定距离处接触互连，从而允许电接触，而不必中断其中最有效的应力衬垫膜。 还公开了将扩散电连接到互连的方法的几个实施例。

公开(公告)号：US07512908B2

公开(公告)日：2009-03-31

申请号：US11450610

申请日：2006-06-09

申请人： Hussein I. Hanafi ,  Richard Q. Williams

发明人： Hussein I. Hanafi ,  Richard Q. Williams

IPC分类号： G06F17/50 ,  G06F9/45 ,  G11C16/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C8/08 ,  G11C11/413

摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.

摘要翻译： 本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。 具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高 以将细胞稳定性提高到所需水平。 具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。 然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

公开(公告)号：US20080169507A1

公开(公告)日：2008-07-17

申请号：US12053658

申请日：2008-03-24

申请人： Edward J. Nowak ,  Richard Q. Williams

发明人： Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L27/12 ,  H01L29/00

CPC分类号： H01L29/8605 ,  H01L27/016 ,  H01L27/0802 ,  H01L29/66166

摘要： A semiconductor resistor, method of making the resistor and method of making an IC including resistors. Buried wells are formed in the silicon substrate of a silicon on insulator (SOI) wafer. At least one trench is formed in the buried wells. Resistors are formed along the sidewalls of the trench and, where multiple trenches form pillars, in the pillars between the trenches by doping the sidewalls with an angled implant. Resistor contacts are formed to the buried well at opposite ends of the trenches and pillars, if any.

摘要翻译： 半导体电阻器，制造电阻器的方法和制造包括电阻器的IC的方法。 掩埋阱形成在绝缘体上硅（SOI）晶片的硅衬底中。 在埋井中形成至少一个沟槽。 电阻器沿着沟槽的侧壁形成，并且在多个沟槽形成支柱的情况下，通过用成角度的植入物掺杂侧壁，在沟槽之间的支柱中形成电阻器。 如果有的话，在沟槽和支柱的相对两端形成电阻触点到掩埋井。

公开(公告)号：US07327008B2

公开(公告)日：2008-02-05

申请号：US10905857

申请日：2005-01-24

申请人： Richard Q. Williams

发明人： Richard Q. Williams

IPC分类号： H01L29/00

CPC分类号： H01L21/76243

摘要： The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said crystal lattice in the first region; and a second structure surrounding the first structure for preventing lattice stress from propagating outward from the first region of the substrate. The present invention also provides various methods for forming the semiconductor structure as well as other like structures.

摘要翻译： 本发明提供一种包括具有晶格的基板的半导体结构; 形成在所述基板的第一区域中的第一结构，所述第一结构至少包括在所述第一区域中在所述晶格中产生晶格应力的异质结构; 以及围绕所述第一结构的第二结构，用于防止晶格应力从所述衬底的所述第一区域向外传播。 本发明还提供了用于形成半导体结构以及其它类似结构的各种方法。