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172 条记录 (耗时 0.03 秒)

    Integrated circuit having a base structure and a nanostructure
    42.
    发明申请
    Integrated circuit having a base structure and a nanostructure 审中-公开
    具有基底结构和纳米结构的集成电路

    公开(公告)号：US20090251968A1

    公开(公告)日：2009-10-08

    申请号：US12099522

    申请日：2008-04-08

    申请人： Christoph Andreas Kleint ,  Josef Willer

    发明人： Christoph Andreas Kleint ,  Josef Willer

    IPC分类号： H01L21/00 ,  G11C16/04

    CPC分类号： H01L27/11578 ,  H01L27/11582

    摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.

    摘要翻译： 在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向 作为基础结构。

    Integrated circuit including resistivity changing memory cells
    44.
    发明授权
    Integrated circuit including resistivity changing memory cells 失效
    集成电路包括电阻率变化记忆单元

    公开(公告)号：US07538411B2

    公开(公告)日：2009-05-26

    申请号：US11411994

    申请日：2006-04-26

    申请人： Josef Willer ,  Klaus-Dieter Ufert

    发明人： Josef Willer ,  Klaus-Dieter Ufert

    IPC分类号： H01L29/00

    CPC分类号： H01L45/14 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/32 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1683

    摘要： Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.

    摘要翻译： 字线堆叠在衬底表面上彼此间隔一定距离平行排列。 位线横向于彼此间隔一定距离的字线堆栈布置。 源极/漏极区域形成为字线堆叠附近的掺杂区域。 电阻层设置在多个源极/漏极区域和位线之间，并且由具有通过施加电压切换的电阻的材料形成。 源极线平行于字线堆栈布置，使得它们连接更多个源极/漏极区域。

    Integrated Circuit Having NAND Memory Cell Strings
    45.
    发明申请
    Integrated Circuit Having NAND Memory Cell Strings 有权
    具有NAND存储器单元串的集成电路

    公开(公告)号：US20090097317A1

    公开(公告)日：2009-04-16

    申请号：US11872655

    申请日：2007-10-15

    申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    IPC分类号： G11C16/00 ,  H01L21/336 ,  H01L29/788

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

    摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

    摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

    Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module
    47.
    发明申请
    Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module 审中-公开
    集成电路，电池，电池布置，集成电路的制造方法，电池的制造方法，存储器模块

    公开(公告)号：US20080237694A1

    公开(公告)日：2008-10-02

    申请号：US11728960

    申请日：2007-03-27

    申请人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L29/513

    摘要： The invention relates to integrated circuits, to a cell, to a cell arrangement, to a method for manufacturing an integrated circuit, to a method for manufacturing a cell, and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a cell, the cell including a low-k dielectric layer, a first high-k dielectric layer disposed above the low-k dielectric layer, a charge trapping layer disposed above the first high-k dielectric layer, and a second high-k dielectric layer disposed above the charge trapping layer.

    摘要翻译： 本发明涉及集成电路，单元，单元布置，集成电路的制造方法，单元的制造方法以及存储器模块。 在本发明的实施例中，提供了具有单元的集成电路，该单元包括低k电介质层，设置在低k电介质层上方的第一高k电介质层，设置在第一 高k电介质层和设置在电荷捕获层上方的第二高k电介质层。

    Capacitorless 1-transistor DRAM cell and fabrication method
    49.
    发明授权
    Capacitorless 1-transistor DRAM cell and fabrication method 有权
    电容式1晶体管DRAM单元及其制造方法

    公开(公告)号：US07341904B2

    公开(公告)日：2008-03-11

    申请号：US11367731

    申请日：2006-03-03

    申请人： Josef Willer

    发明人： Josef Willer

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/1203 ,  H01L27/108 ,  H01L27/10876 ,  H01L29/7841 ,  Y10S257/906

    摘要： A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor material such that a vertical strip of semiconductor material remains along a sidewall of the dielectric material. A lower portion of the semiconductor body adjacent the sidewall of the dielectric material is doped. A gate dielectric layer is formed over the vertical strip of semiconductor material and a gate electrode is arranged in the cutout.

    摘要翻译： 通过在半导体本体中形成沟槽来制造半导体器件。 电介质材料的区域形成在沟槽的至少下部内。 掺杂半导体本体的上部。 在半导体材料中形成切口，使得半导体材料的垂直条沿着电介质材料的侧壁保留。 与电介质材料的侧壁相邻的半导体本体的下部被掺杂。 栅电介质层形成在半导体材料的垂直条上，栅电极设置在切口中。

    Memory device and a method of forming a memory device
    50.
    发明申请
    Memory device and a method of forming a memory device 审中-公开
    存储装置和形成存储装置的方法

    公开(公告)号：US20070284650A1

    公开(公告)日：2007-12-13

    申请号：US11448134

    申请日：2006-06-07

    申请人： Josef Willer

    发明人： Josef Willer

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A memory device includes active regions extending in a first direction, the active regions being formed in a semiconductor substrate. Transistors are formed in the active regions, including a first and a second source/drain region, a channel formed between the first and the second source/drain region, a gate electrode, and a charge storage layer stack disposed between the gate electrode and the channel, where adjacent active regions are isolated from each other by fin isolation grooves. Wordlines extend in a second direction, and each wordline is connected with a plurality of gate electrodes that are assigned to different active regions. The active regions are formed as ridges in the semiconductor substrate, with the word lines and the charge storing layer stack being disposed adjacent to at least two sides of each of the active regions. Each of the ridges has a top portion and a bottom portion, where the maximum width of the top portion is larger than the minimum width of the bottom portion.

    摘要翻译： 存储器件包括沿第一方向延伸的有源区，有源区形成在半导体衬底中。 晶体管形成在有源区域中，包括第一和第二源极/漏极区域，形成在第一和第二源极/漏极区域之间的沟道，栅极电极和电荷存储层堆叠，其设置在栅极电极和第二源极/漏极区域之间 通道，其中相邻的有源区域通过散热片隔离槽相互隔离。 字线在第二方向上延伸，并且每条字线与分配给不同有效区域的多个栅电极连接。 有源区域在半导体衬底中形成为脊，其中字线和电荷存储层堆叠被布置为与每个有源区域的至少两侧相邻。 每个脊具有顶部和底部，其中顶部的最大宽度大于底部的最小宽度。