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    Integrated Circuit Having NAND Memory Cell Strings
    2.
    发明申请
    Integrated Circuit Having NAND Memory Cell Strings 有权
    具有NAND存储器单元串的集成电路

    公开(公告)号：US20090097317A1

    公开(公告)日：2009-04-16

    申请号：US11872655

    申请日：2007-10-15

    申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    IPC分类号： G11C16/00 ,  H01L21/336 ,  H01L29/788

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

    摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

    摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

    Memory device and method providing logic connections for data transfer
    4.
    发明授权
    Memory device and method providing logic connections for data transfer 有权
    提供用于数据传输的逻辑连接的存储器件和方法

    公开(公告)号：US07940575B2

    公开(公告)日：2011-05-10

    申请号：US12058191

    申请日：2008-03-28

    申请人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

    发明人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

    IPC分类号： G11C7/10 ,  G11C8/12 ,  G11C16/06

    CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

    摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

    摘要翻译： 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

    Memory Device and Method Providing Logic Connections for Data Transfer
    5.
    发明申请
    Memory Device and Method Providing Logic Connections for Data Transfer 有权
    为数据传输提供逻辑连接的存储器件和方法

    公开(公告)号：US20090244949A1

    公开(公告)日：2009-10-01

    申请号：US12058191

    申请日：2008-03-28

    申请人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

    发明人： Roberto Ravasio ,  Andreas Kux ,  Detlev Richter ,  Girolamo Gallo ,  Josef Willer ,  Ramirez Xavier Veredas

    IPC分类号： G11C5/06

    CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

    摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.

    摘要翻译： 在一个实施例中，提供了一种用于在存储器件中传送数据的方法。 该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接 通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。 数据通过使用可控连接的逻辑连接进行传输。 同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

    Integrated circuit having NAND memory cell strings
    7.
    发明授权
    Integrated circuit having NAND memory cell strings 有权
    具有NAND存储单元串的集成电路

    公开(公告)号：US07778073B2

    公开(公告)日：2010-08-17

    申请号：US11872655

    申请日：2007-10-15

    申请人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    发明人： Josef Willer ,  Franz Hofmann ,  Detlev Richter ,  Nicolas Nagel

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/11568

    摘要： Embodiments of the present invention relate generally to integrated circuits and methods for manufacturing an integrated circuit. In an embodiment of the invention, an integrated circuit having a memory cell is provided. The memory cell may include a trench in a carrier, a charge trapping layer structure in the trench, the charge trapping layer structure comprising at least two separate charge trapping regions, electrically conductive material at least partially filled in the trench, and source/drain regions next to the trench.

    摘要翻译： 本发明的实施例一般涉及用于制造集成电路的集成电路和方法。 在本发明的实施例中，提供了具有存储单元的集成电路。 存储单元可以包括载体中的沟槽，沟槽中的电荷俘获层结构，电荷俘获层结构包括至少两个分离的电荷俘获区，至少部分填充在沟槽中的导电材料以及源/漏区 旁边的沟槽。

    Integrated circuit having a base structure and a nanostructure
    10.
    发明申请
    Integrated circuit having a base structure and a nanostructure 审中-公开
    具有基底结构和纳米结构的集成电路

    公开(公告)号：US20090251968A1

    公开(公告)日：2009-10-08

    申请号：US12099522

    申请日：2008-04-08

    申请人： Christoph Andreas Kleint ,  Josef Willer

    发明人： Christoph Andreas Kleint ,  Josef Willer

    IPC分类号： H01L21/00 ,  G11C16/04

    CPC分类号： H01L27/11578 ,  H01L27/11582

    摘要： In an embodiment, an integrated circuit may include a metallically conductive structure, a base structure having a crystal orientation, the base structure being adjacent to the metallically conductive structure, and a nanostructure disposed on the base structure, the nanostructure having substantially the same crystal orientation as the base structure.

    摘要翻译： 在一个实施例中，集成电路可以包括金属导电结构，具有晶体取向的基底结构，与金属导电结构相邻的基底结构，以及设置在基底结构上的纳米结构，纳米结构具有基本上相同的晶体取向 作为基础结构。