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公开(公告)号：US20060197976A1
公开(公告)日：2006-09-07
申请号：US11334593
申请日：2006-01-19
申请人： Koji Oka
发明人： Koji Oka
IPC分类号： G06F3/12
CPC分类号： H04N1/00278 , H04N1/32368 , H04N2201/0015 , H04N2201/0027 , H04N2201/0084 , H04N2201/3298 , H04N2201/33321 , H04N2201/33335
摘要： A printing control apparatus includes an image pickup unit, a storing unit, a receiver, a display unit, a selector, a communicator, and a control unit therefor. The control unit is configured to calculate the number of image data possible to be included in printing control information based on at least one item in a power value received from a printing device and selected by the selector, the image data selected by the selector and a capacity of a memory used for communication of the printing control apparatus or/and the printing device, and to generate at least one printing control information according to the calculated number of the image data.
摘要翻译： 打印控制装置包括图像拾取单元，存储单元，接收器，显示单元，选择器，通信器及其控制单元。 控制单元被配置为基于从打印设备接收并由选择器选择的功率值中的至少一个项目计算可包括在打印控制信息中的图像数据的数量，由选择器选择的图像数据和 用于打印控制装置或/和打印装置的通信的存储器的容量，并且根据计算出的图像数据的数量生成至少一个打印控制信息。
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公开(公告)号：US06310492B1
公开(公告)日：2001-10-30
申请号：US09561962
申请日：2000-05-01
申请人： Heiji Ikoma , Yoshitsugu Inagaki , Hiroyuki Konishi , Koji Oka , Akira Matsuzawa
发明人： Heiji Ikoma , Yoshitsugu Inagaki , Hiroyuki Konishi , Koji Oka , Akira Matsuzawa
IPC分类号： H03K190175
CPC分类号： H03K19/00361 , H03K19/0016 , H03K19/00315
摘要： In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter has a P-channel FET (field effect transistor) with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET is connected to the power supply and a back gate electrode of the P-channel FET is in direct connection with the aforesaid source electrode. The P-channel FET is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET at the zero level.
摘要翻译： 为了降低功耗，关闭数字电路部分的电源，使得电源的输出电压变为零电平。 CMOS（互补金属氧化物半导体）反相器具有由P型多晶硅形成的栅电极的P沟道FET（场效应晶体管）。 P沟道FET的源电极连接到电源，P沟道FET的背栅极与前述源极直接连接。 当在低功耗模式下关闭电源时，P沟道FET被置于不用作晶体管的状态。 然而，为了防止P沟道FET在该模式中发生特性劣化，提供了一种下拉开关，其能够在该模式中固定P沟道FET的栅电极的电压 零级。
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公开(公告)号：US10122957B2
公开(公告)日：2018-11-06
申请号：US14816394
申请日：2015-08-03
申请人： Koji Oka
发明人： Koji Oka
摘要： An imaging apparatus that records separately shot two images as one image file includes a clip image shooting mode that creates the one image file having one of the separately shot two images as a supplemental image of the other of the separately shot two images as a main image.
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44.发明授权公开(公告)号：US07834701B2
公开(公告)日：2010-11-16
申请号：US12519291
申请日：2008-05-28
申请人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
发明人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
IPC分类号： H03F3/04
CPC分类号： H03F3/45475 , H03F1/0261 , H03F1/34 , H03F3/3022 , H03F3/347 , H03F3/45928 , H03F3/68 , H03F2203/45136
摘要： A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
摘要翻译： 多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中，用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压， 运算放大器OpAS，偏置电压VIr从内置差分放大器电路的非反相输入VIP输入，内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA，从而获得电压跟随器。 此外，设置多个输出放大器电路OA2至OAn，使得其输入端连接到差分放大器电路DA的输出端，并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。
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公开(公告)号：US07750939B2
公开(公告)日：2010-07-06
申请号：US11377370
申请日：2006-03-17
申请人： Toshiyuki Kobayashi , Takayoshi Shimizu , Koji Oka
发明人： Toshiyuki Kobayashi , Takayoshi Shimizu , Koji Oka
CPC分类号： H04N5/23203 , H04N1/00204 , H04N5/23241 , H04N2101/00 , H04N2201/0075 , H04N2201/0084
摘要： An image photographing device (1), which converts an optical image of a subject into an electric signal by an image pick up device, and stores image data by the electric signal in an information recording medium (21), includes a communication interface (25), which communicates the image data, a determination device (31), which determines whether a device connected to the communication interface is an external device (2) or a release device (3), a communication process device (10), which conducts a communication process with the external device if the determination device determines that the external device is connected, and a photographing process device (10), which conducts a photographing process if the determination device determines that the release device is connected.
摘要翻译： 一种图像拍摄装置（1），其通过图像拾取装置将被摄体的光学图像转换为电信号，并且通过电信号将图像数据存储在信息记录介质（21）中，包括通信接口（25） ），确定连接到所述通信接口的设备是外部设备（2）还是释放设备（3）的确定设备（31），所述通信处理设备（10）执行 如果所述确定装置确定所述外部装置被连接，则与所述外部装置的通信处理;以及拍摄处理装置，如果所述确定装置确定所述释放装置被连接，则进行拍摄处理。
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46.发明申请公开(公告)号：US20100045382A1
公开(公告)日：2010-02-25
申请号：US12519291
申请日：2008-05-28
申请人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
发明人： Tsuyoshi Matsushita , Koji Oka , Junichi Naka
IPC分类号： H03F3/34
CPC分类号： H03F3/45475 , H03F1/0261 , H03F1/34 , H03F3/3022 , H03F3/347 , H03F3/45928 , H03F3/68 , H03F2203/45136
摘要： A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA2 via respective capacitors C. In a bias circuit Bias for supplying a bias voltage such as a signal ground of the analog signals to the analog signal processing circuit ANA2, in an operational amplifier OpAS, a bias voltage VIr is input from a non-inverting input VIP of a built-in differentiate amplifier circuit, an output terminal of the built-in output amplifier circuit OA1 is connected to an inverting input terminal VIM of the differentiate amplifier circuit DA, and thereby a voltage follower is obtained. Furthermore, a plurality of output amplifier circuits OA2 through OAn are provided so that input terminals thereof are connected to output terminals of the differential amplifier circuit DA, and the output terminals are connected to input terminals IN1 through INn of the analog signal processing circuit ANA2.
摘要翻译： 多个模拟信号通过各自的电容器C输入到模拟信号处理电路ANA2的输入端子。在偏置电路Bias中，用于向模拟信号处理电路ANA2提供诸如模拟信号的信号地的偏置电压， 运算放大器OpAS，偏置电压VIr从内置差分放大器电路的非反相输入VIP输入，内置输出放大器电路OA1的输出端连接到差分放大器的反相输入端VIM 放大电路DA，从而获得电压跟随器。 此外，设置多个输出放大器电路OA2至OAn，使得其输入端连接到差分放大器电路DA的输出端，并且输出端连接到模拟信号处理电路ANA2的输入端IN1至INn。
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公开(公告)号：US20090155431A1
公开(公告)日：2009-06-18
申请号：US12226862
申请日：2007-04-09
申请人： Takayuki Date , Masahiro Honda , Koji Oka , Shigeki Hayata , Shinji Matsumoto , Tatsumi Ootakara
发明人： Takayuki Date , Masahiro Honda , Koji Oka , Shigeki Hayata , Shinji Matsumoto , Tatsumi Ootakara
摘要： An object of the present invention is to provide a straight stick-shaped snacks and a method for producing the same.The present invention provides a method for producing a stick-shaped snack from a string-like dough 10 containing a cereal flour as a principal component, the method including: a baking step S6 of baking the string-like dough 10 provided with a plurality of non-through cuts 15 formed therein across the longitudinal direction and impregnated with lye, the string-like dough 10 being mounted on a heating surface; and a cutting step S7 of cutting the baked string-like dough 40 at the cuts 15 to thereby form stick-shaped pastries 40.
摘要翻译： 本发明的目的在于提供一种直棒状小吃及其制造方法。 本发明提供一种以包含谷物粉为主要成分的线状面团10制作棒状小吃的方法，该方法包括：烘烤步骤S6，烘烤具有多个 穿过纵向方向形成的非贯穿切口15，并浸渍有碱液，线状面团10安装在加热表面上; 以及切割步骤S7，其在切口15处切割烘烤的线状面团40，从而形成棒状糕点40。
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公开(公告)号：US07019676B2
公开(公告)日：2006-03-28
申请号：US10864376
申请日：2004-06-10
申请人： Heiji Ikoma , Koji Oka
发明人： Heiji Ikoma , Koji Oka
摘要： A current output type D/A converter for converting a digital signal into an analog signal comprises a control signal input terminal for receiving a control signal supplied from the outside, and an output load element having a switching mechanism for electrically connecting or disconnecting the output load element to/from an analog output node on the basis of the control signal applied to the control input terminal.
摘要翻译： 用于将数字信号转换为模拟信号的电流输出型D / A转换器包括用于接收从外部提供的控制信号的控制信号输入端子和具有用于电连接或断开输出负载的切换机构的输出负载元件 基于施加到控制输入端子的控制信号，来自/来自模拟输出节点的元件。
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49.发明申请Digital camera, method for controlling digital camera, computer program for controlling a digital camera, signal for controlling digital camera and image playback apparatus 审中-公开数码相机，数码相机控制方法，控制数码相机的计算机程序，控制数码相机的信号和图像播放装置公开(公告)号：US20050012828A1
公开(公告)日：2005-01-20
申请号：US10892307
申请日：2004-07-16
申请人： Koji Oka
发明人： Koji Oka
摘要： A digital camera having a temporary memory for driving a display. The temporary memory is fed image data from an external or internal non-volatile memory. The temporary memory is controlled so that it stores the image on display along with a predetermined number of previously viewed and to-be-viewed images. In response to a frame advance command, one image is deleted from temporary memory and another image is added to the temporary memory. The digital camera is configured to temporarily interrupt image uploading when the operator exercises a command, such as a frame advance command.
摘要翻译： 一种具有用于驱动显示器的临时存储器的数字照相机。 临时存储器从外部或内部非易失性存储器馈送图像数据。 控制临时存储器，使其与显示的图像一起存储预定数量的先前观看和待观看图像。 响应于帧提前命令，从临时存储器中删除一个图像，并将另一图像添加到临时存储器。 数码相机被配置为当操作者执行诸如帧提前命令的命令时临时中断图像上传。
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公开(公告)号：US06700524B2
公开(公告)日：2004-03-02
申请号：US10256238
申请日：2002-09-27
申请人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
发明人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
IPC分类号： H03M138
CPC分类号： H03M1/007 , H03M1/0695 , H03M1/44
摘要： An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.
摘要翻译： A / D转换器包括一个其中多个流水线级串联连接的流水线阵列，每个流水线级对所输入的模拟电压进行流水线操作以输出数字电压; 根据指示分辨率的位数控制信号，输出指示每个流水线级的操作是否应被执行或停止的位数选择信号的位数控制电路; 以及根据位数控制信号补偿要输出的数字值的校正电路。 因此，当系统请求的A / D转换器的分辨率改变时，仅在实现所请求的分辨率所需的流水线阶段在其它流水线级停止的同时被操作，从而降低了A / D转换器，同时避免了A / D转换器的输出故障。
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