公开(公告)号：US09466564B1

公开(公告)日：2016-10-11

申请号：US14692762

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L23/522 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 栅极结构上的第一个硬掩模; 以及栅极结构上的第二硬掩模，其中所述第一硬掩模与所述第二硬掩模的两侧相邻，并且所述第一硬掩模和所述第一硬掩模包括氮化硅。

公开(公告)号：US20160276260A1

公开(公告)日：2016-09-22

申请号：US14682124

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

Abstract translation: 公开了一种用于制造金属互连结构的方法。 该方法包括以下步骤：提供其上具有第一金属间电介质（IMD）层的衬底; 在第一IMD层中形成金属互连; 去除第一IMD层的一部分; 形成邻近所述金属互连的间隔物; 并且使用间隔物作为掩模来去除第一IMD层的一部分，以在第一IMD层中形成开口。

公开(公告)号：US09448471B2

公开(公告)日：2016-09-20

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US09406521B1

公开(公告)日：2016-08-02

申请号：US14793692

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L21/308 ,  H01L27/088 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

Abstract translation: 半导体器件及其形成方法，所述半导体器件包括衬底，多个鳍状结构和绝缘层。 衬底具有鳍状场效应晶体管（finFET）区域，第一区域，第二区域和第三区域。 第一区域，第二区域和第三区域分别具有第一表面，第二表面和第三表面，其中第一表面相对高于第二表面，而第二表面相对高于第三表面。 鳍状结构设置在鳍状场效应晶体管区域的表面上。 绝缘层覆盖第一表面，第二表面和第三表面。

公开(公告)号：US09122835B2

公开(公告)日：2015-09-01

申请号：US14151785

申请日：2014-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F7/70441 ,  G03F7/70466

Abstract: A method for generating a layout pattern of integrated circuit (IC) is provided. First, feature patterns are provided to a computer system and dummy pad patterns are generated in a space among the feature patterns. The layout pattern is then split into first feature patterns and second feature patterns. The dimensions of the first feature patterns are less than the dimensions of the second feature patterns. Afterwards, the dummy pad patterns are combined with the second features pattern to form a combined pattern. Then, mandrel patterns are generated in a space between the first feature patterns and the geometric patterns are generated according to the positions of the first feature patterns. Finally, the combined pattern, the mandrel patterns, and the geometric patterns are respectively outputted to form a first, a second, and a third photomasks.

Abstract translation: 提供了一种用于生成集成电路（IC）的布局图案的方法。 首先，将特征图案提供给计算机系统，并且在特征图案之间的空间中生成虚拟垫图案。 然后将布局图案分割成第一特征图案和第二特征图案。 第一特征图案的尺寸小于第二特征图案的尺寸。 之后，将虚拟焊盘图形与第二特征图案组合以形成组合图案。 然后，在第一特征图案之间的空间中产生心轴图案，并且根据第一特征图案的位置生成几何图案。 最后，分别输出组合图案，心轴图案和几何图案以形成第一，第二和第三光掩模。

公开(公告)号：US09054187B2

公开(公告)日：2015-06-09

申请号：US14089771

申请日：2013-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

公开(公告)号：US20130299951A1

公开(公告)日：2013-11-14

申请号：US13942258

申请日：2013-07-15

Applicant: United Microelectronics Corp.

Inventor： Yu-Cheng Tung

IPC: H01L29/06

CPC classification number: H01L29/06 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/76232 ,  H01L29/66818 ,  H01L29/7853

Abstract: Provided is a fin structure including a fin and two insulating layers. The fin is disposed on a substrate, wherein an upper portion is narrower than a lower portion of the fin, and the fin has an inverse T shape. The insulating layers are disposed at two sides of the fin and at least expose the upper portion of the fin.

Abstract translation: 提供一种翅片结构，其包括翅片和两个绝缘层。 翅片设置在基板上，其中上部比翅片的下部窄，并且翅片具有逆T形状。 绝缘层设置在翅片的两侧，并且至少暴露翅片的上部。

公开(公告)号：US11721552B2

公开(公告)日：2023-08-08

申请号：US17561989

申请日：2021-12-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L21/027 ,  H01L21/033 ,  H10B12/00 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H10B12/03 ,  H01L21/32139

Abstract: A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

公开(公告)号：US11450747B2

公开(公告)日：2022-09-20

申请号：US17218112

申请日：2021-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

IPC: H01L29/04 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00 ,  H01L33/00 ,  H01L33/12 ,  H01L33/16 ,  H01L29/165

Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

公开(公告)号：US11158623B2

公开(公告)日：2021-10-26

申请号：US16721940

申请日：2019-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/02 ,  H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.