公开(公告)号：US09448471B2

公开(公告)日：2016-09-20

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  G03F7/20 ,  H01L21/027

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US09482964B2

公开(公告)日：2016-11-01

申请号：US14279039

申请日：2014-05-15

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70516

Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

Abstract translation: 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设的偏移量b1。 预置偏移量a1和b1不相等。

公开(公告)号：US09305884B1

公开(公告)日：2016-04-05

申请号：US14498217

申请日：2014-09-26

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033 ,  H01L21/66

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。

公开(公告)号：US20160018728A1

公开(公告)日：2016-01-21

申请号：US14335949

申请日：2014-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Teng-Chin Kuo ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F1/38 ,  H01L21/027 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03F7/20 ,  H01L21/0274

Abstract: The present invention provides a photo-mask for manufacturing structures on a semiconductor substrate, which comprises a photo-mask substrate, a first pattern, a second pattern and a forbidden pattern. A first active region, a second active region are defined on the photo-mask substrate, and a region other than the first active region and the second active region are defined as a forbidden region. The first pattern is disposed in the first active region and corresponds to a first structure on the semiconductor substrate. The second pattern is disposed in the second active region and corresponds to a second structure on the semiconductor substrate. The forbidden pattern is disposed in the forbidden region, wherein the forbidden pattern has a dimension beyond resolution capability of photolithography and is not used to form any corresponding structure on the semiconductor substrate. The present invention further provides a method of manufacturing semiconductor structures.

Abstract translation: 本发明提供一种用于在半导体衬底上制造结构的光掩模，其包括光掩模衬底，第一图案，第二图案和禁止图案。 第一有源区，第二有源区被限定在光掩模基板上，除了第一有源区和第二有源区之外的区域被定义为禁止区。 第一图案设置在第一有源区中并对应于半导体衬底上的第一结构。 第二图案设置在第二有源区域中，并且对应于半导体衬底上的第二结构。 禁止图案设置在禁止区域中，其中禁止图案具有超过光刻分辨能力的尺寸，并且不用于在半导体基板上形成任何相应的结构。 本发明还提供一种制造半导体结构的方法。

公开(公告)号：US20150362905A1

公开(公告)日：2015-12-17

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G05B19/18 ,  G03F7/20

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。

公开(公告)号：US20160103396A1

公开(公告)日：2016-04-14

申请号：US14512484

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70058 ,  G03F7/70466 ,  G03F7/70625

Abstract: A double patterning method comprises the following steps. First of all, a target layer and a mask layer stacked thereon are provided. Next, a first pattern opening is formed in the mask layer, and a width of the first pattern opening is measured to obtain a measuring value. Then, a second pattern opening is formed in the mask layer based on the measuring value, wherein the second pattern opening and the first pattern opening are co-planar. Finally, a bias trimming process is performed to trim the first pattern opening and the second pattern opening.

Abstract translation: 双重图案化方法包括以下步骤。 首先，提供堆叠在其上的目标层和掩模层。 接下来，在掩模层中形成第一图案开口，并且测量第一图案开口的宽度以获得测量值。 然后，基于测量值在掩模层中形成第二图案开口，其中第二图案开口和第一图案开口是共面的。 最后，执行偏置修剪处理以修剪第一图案开口和第二图案开口。

公开(公告)号：US20150293461A1

公开(公告)日：2015-10-15

申请号：US14279039

申请日：2014-05-15

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70516

Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

Abstract translation: 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设偏移量b1。 预置偏移量a1和b1不相等。

公开(公告)号：US09400435B2

公开(公告)日：2016-07-26

申请号：US14457136

申请日：2014-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Teng-Chin Kuo ,  Chia-Hung Wang ,  Tuan-Yen Yu ,  Yuan-Chi Pai ,  Chun-Chi Yu

IPC: G03F7/20 ,  G03F9/00 ,  G05B19/18 ,  G03F1/42

CPC classification number: G03F7/70633 ,  G03F1/42 ,  G03F7/70491 ,  G05B19/188 ,  G05B2219/45027 ,  G05B2219/45031

Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.

Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。

公开(公告)号：US20160172308A1

公开(公告)日：2016-06-16

申请号：US15052508

申请日：2016-02-24

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Teng-Chin Kuo ,  Yi-Ting Chen

IPC: H01L23/544 ,  H01L21/033 ,  H01L23/532

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L22/12 ,  H01L22/20 ,  H01L23/53271 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract translation: 描述了应用于包括第一光刻步骤，第一蚀刻步骤，第二光刻步骤和第二蚀刻步骤的LELE型双重图案化光刻（DPL）工艺的覆盖标记。 覆盖标记包括由第一光刻步骤限定的当前层的先前层，第二x方向和y方向图案的第一x方向图案和第一y方向图案，以及第三x方向和y方向图案， 由第二光刻步骤限定的当前层的方向图案。 第二x方向图案和第三x方向图案交替排列在第一x方向图案旁边。 第二y方向图案和第三y方向图案交替排列在第一y方向图案旁边。

公开(公告)号：US20160126194A1

公开(公告)日：2016-05-05

申请号：US14533108

申请日：2014-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chang Hsu ,  Teng-Chin Kuo ,  En-Chiuan Liou

IPC: H01L23/544 ,  H01L21/311 ,  G01B11/00

CPC classification number: H01L21/311 ,  G01B11/002 ,  G03F7/70633 ,  G03F7/70683

Abstract: The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped.

Abstract translation: 本发明提供一种测量标记结构，包括多个内部图案，内部图案沿着第一方向布置，外部图案位于围绕内部图案的位置，外部图案是矩形框形。