公开(公告)号：US20120216195A1

公开(公告)日：2012-08-23

申请号：US13459167

申请日：2012-04-28

申请人： Lisa C. Heller

发明人： Lisa C. Heller

IPC分类号： G06F9/455 ,  G06F9/312

CPC分类号： G06F9/30087 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30185 ,  G06F9/45533 ,  G06F9/52

摘要： A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock.

摘要翻译： 提供系统序列化功能以便于允许多个处理器更新相同资源的那些环境中的处理。 系统序列化功能用于在多处理环境中促进处理，其中客人和主机使用锁来提供序列化。 系统序列化功能包括在主机获取锁定之后发出的诊断指令，消除了客人获取锁定的需要。

公开(公告)号：US08151083B2

公开(公告)日：2012-04-03

申请号：US11972713

申请日：2008-01-11

申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

IPC分类号： G06F12/00

CPC分类号： G06F12/1475 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30145 ,  G06F12/00 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/68

摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

公开(公告)号：US08117417B2

公开(公告)日：2012-02-14

申请号：US11972694

申请日：2008-01-11

申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/1009 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/455 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/1475

摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified.

摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 从段表获得的段表条目包含格式控制字段。 如果启用格式控制字段，则从段表条目获取主存储器中的大块数据的分段帧绝对地址。 大块内的每4K字节的数据块具有关联的存储密钥。 与虚拟地址相关联的存储操作被执行到期望的数据块。 如果改变记录覆盖字段被禁用，则与期望的4K字节块相关联的存储密钥的改变位被设置为1.然后提供所需的4K字节块已被修改的指示。

公开(公告)号：US08032716B2

公开(公告)日：2011-10-04

申请号：US12037904

申请日：2008-02-26

申请人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

发明人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/1072 ,  G06F12/1475

摘要： A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

摘要翻译： 一种用于提供新的静默状态的系统，方法和计算机程序产品。 该方法包括从系统控制器从启动处理器接收静默请求。 停顿请求被发送到多个处理器。 在系统控制器处接收到通知，处理器已经完成清除其翻译的旁边的缓冲区（TLB）。 一旦系统资源的更新完成，系统控制器就会从启动处理器接收快速静默复位命令。 向处理器指示响应于接收到快速静默复位命令可以丢弃块转换限制，从而允许处理器继续处理而没有块转换限制。

公开(公告)号：US20110119466A1

公开(公告)日：2011-05-19

申请号：US13005659

申请日：2011-01-13

申请人： Timothy J. Slegel ,  Lisa C. Heller ,  Erwin F. Pfeffer ,  Kenneth E. Plambeck

发明人： Timothy J. Slegel ,  Lisa C. Heller ,  Erwin F. Pfeffer ,  Kenneth E. Plambeck

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F9/30047 ,  G06F9/3824 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/683

摘要： An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

摘要翻译： 提供指令来执行与特定地址空间相关联的所选地址转换缓冲器条目（TLB条目）的清除，诸如存储段或存储区域。 缓冲区条目与段表项或区域表项或ASCE地址相关。 该指令可以通过软件仿真，硬件，固件或其组合来实现。

公开(公告)号：US20090216963A1

公开(公告)日：2009-08-27

申请号：US12037177

申请日：2008-02-26

申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Donald W. Schmidt ,  Jaya Srikrishnan ,  Charles F. Webb ,  Leslie W. Wyman

发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Donald W. Schmidt ,  Jaya Srikrishnan ,  Charles F. Webb ,  Leslie W. Wyman

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/00 ,  G06F12/0284 ,  G06F12/109 ,  G06F12/1441 ,  G06F2212/656

摘要： A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed.

摘要翻译： 一种用于提供共享存储器翻译设备的系统，方法和计算机程序产品。 该方法包括在配置下从请求者接收访问存储器地址的请求，在共享存储器转换机制处接收。 确定存储器地址是指共享存储器对象（SMO），SMO可由多个配置访问。 响应于确定存储器地址是指SMO，确定配置是否可以访问SMO。 响应于确定配置可以访问SMO，请求者为SMO提供系统绝对地址并访问SMO。 以这种方式允许在多个配置之间直接互换数据。

公开(公告)号：US20090216928A1

公开(公告)日：2009-08-27

申请号：US12037904

申请日：2008-02-26

申请人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

发明人： Lisa C. Heller ,  Michael F. Fee ,  Christine C. Jones

IPC分类号： G06F13/24

CPC分类号： G06F12/1027 ,  G06F12/1072 ,  G06F12/1475

摘要： A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.

摘要翻译： 一种用于提供新的静默状态的系统，方法和计算机程序产品。 该方法包括从系统控制器从启动处理器接收静默请求。 停顿请求被发送到多个处理器。 在系统控制器处接收到通知，处理器已经完成清除其翻译的旁边的缓冲区（TLB）。 一旦系统资源的更新完成，系统控制器就会从启动处理器接收快速静默复位命令。 向处理器指示响应于接收到快速静默复位命令可以丢弃块转换限制，从而允许处理器继续处理而没有块转换限制。

公开(公告)号：US20090193214A1

公开(公告)日：2009-07-30

申请号：US11972718

申请日：2008-01-11

申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F9/30043 ,  G06F9/30145

摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained containing an opcode for a frame management instruction identifying a first and second general register. Clear frame information is obtained from the first general register having a frame size field indicating whether a storage frame is a small or large block of data. The second general register contains an operand address of a storage frame. If the storage frame is a small block, all bytes of the small block of data are set to zero. If the storage frame is a large block of data, an operand address of an initial first block of data within the large block is obtained from the second general register. All data of all blocks within the large block are cleared starting from the initial first block.

摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得包含识别第一和第二通用寄存器的帧管理指令的操作码的机器指令。 从具有指示存储帧是小数据块还是大数据块的帧大小字段的第一通用寄存器获得清除帧信息。 第二个通用寄存器包含存储帧的操作数地址。 如果存储帧是小块，则小块数据的所有字节都被设置为零。 如果存储帧是大数据块，则从第二通用寄存器获得大块内的初始第一数据块的操作数地址。 大块内的所有块的所有数据从初始第一块开始清零。

公开(公告)号：US20090187732A1

公开(公告)日：2009-07-23

申请号：US11972715

申请日：2008-01-11

申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/651 ,  G06F2212/652

摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address.

摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和区域第一表，区域秒表，区域第三表或段表中的任何一个的初始起始地址。 基于获得的初始起始地址，获得包含格式控制和DAT保护字段的段表条目。 如果格式控制字段被使能，则从转换表条目获得主存储器中的大块数据的段帧绝对地址。 分段帧绝对地址与虚拟地址的页索引部分和字节索引部分组合，以形成所需数据块的转换地址。 如果DAT保护字段未被使能，则获取和存储被允许被转换的虚拟地址寻址的所需数据块。

公开(公告)号：US20090187728A1

公开(公告)日：2009-07-23

申请号：US11972694

申请日：2008-01-11

申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/34

CPC分类号： G06F12/1009 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/455 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/1475

摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified.

摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 从段表获得的段表条目包含格式控制字段。 如果启用格式控制字段，则从段表条目获取主存储器中的大块数据的分段帧绝对地址。 大块内的每4K字节的数据块具有关联的存储密钥。 与虚拟地址相关联的存储操作被执行到期望的数据块。 如果改变记录覆盖字段被禁用，则与期望的4K字节块相关联的存储密钥的改变位被设置为1.然后提供所需的4K字节块已被修改的指示。