-
41.发明授权Word line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same 有权用于非易失性存储器件和存储器件的字线升压系统和方法以及使用它的基于处理器的系统公开(公告)号：US07924616B2
公开(公告)日：2011-04-12
申请号：US11795357
申请日：2007-05-04
IPC分类号： G11C16/04
摘要： The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
摘要翻译： 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选择的字线 的阵列驱动晶体管。
-
42.发明申请Word Line Voltage Boost System and Method for Non-Volatile Memory Devices and Memory Devices and Processor-Based System Using Same 有权用于非易失性存储器件和存储器件的字线电压升压系统和方法以及使用其的基于处理器的系统公开(公告)号：US20100128534A1
公开(公告)日：2010-05-27
申请号：US11795357
申请日：2007-05-04
摘要： The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
摘要翻译： 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选字线 的阵列驱动晶体管。
-
公开(公告)号：US20100097856A1
公开(公告)日：2010-04-22
申请号：US12643610
申请日：2009-12-21
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： In a method of operation, a flash memory cell coupled to a bit-line is programmed, a word-line voltage is coupled to the flash memory cell, a first voltage pulse is coupled to a bias transistor coupled between the bit-line and a sense capacitance at a first time to couple the bit-line to the sense capacitance to generate data to indicate the state of the flash memory cell, a second voltage pulse is coupled to the bias transistor at a second time having a second magnitude that is different from a first magnitude of the first voltage pulse, and a third voltage pulse is coupled to the bias transistor at a third time having a third magnitude that is different from the second magnitude of the second voltage pulse. In a method of operation, the second voltage pulse occurs a first delay period after the first voltage pulse and the third voltage pulse occurs a second delay period after the second voltage pulse, the second delay period being different from the first delay period.
摘要翻译： 在一种操作方法中，与位线耦合的快闪存储器单元被编程，字线电压耦合到闪存单元，第一电压脉冲耦合到耦合在位线和 在第一时间感测电容以将位线耦合到感测电容以产生指示闪存单元的状态的数据，第二电压脉冲在具有不同的第二大小的第二时间耦合到偏置晶体管 并且第三电压脉冲在第三时间与具有与第二电压脉冲的第二幅度不同的第三幅度耦合到偏置晶体管。 在一种操作方法中，第二电压脉冲在第一电压脉冲和第三电压脉冲在第二电压脉冲之后发生第二延迟时段之后的第一延迟时段，第二延迟周期不同于第一延迟周期。
-
公开(公告)号：US08264882B2
公开(公告)日：2012-09-11
申请号：US13313379
申请日：2011-12-07
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
-
45.发明授权Technique to reduce FG-FG interference in multi bit NAND flash memory in case of adjacent pages not fully programmed 有权在相邻页面未完全编程的情况下，减少多位NAND闪存中FG-FG干扰的技术公开(公告)号：US08194448B2
公开(公告)日：2012-06-05
申请号：US12647317
申请日：2009-12-24
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3418
摘要： A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell, the method includes checking whether adjacent pages of near memory cells have been programmed. The method may program adjacent pages of near memory cells that have not been programmed.
摘要翻译： 提供了一种在编程NAND闪速存储器中减少浮置栅极 - 浮动栅极干扰的方法。 在对存储器单元的上部页进行编程之前，该方法包括检查邻近存储器单元的相邻页面是否被编程。 该方法可以编程尚未被编程的近的存储器单元的相邻页面。
-
公开(公告)号：US20090219761A1
公开(公告)日：2009-09-03
申请号：US12177972
申请日：2008-07-23
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译： 所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。 在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。 对所选存储单元执行另一个程序验证操作。 如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。 然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。
-
公开(公告)号：US08526238B2
公开(公告)日：2013-09-03
申请号：US12896487
申请日：2010-10-01
CPC分类号： G11C16/3436 , G11C11/56 , G11C11/5628 , G11C16/00 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C16/3481 , G11C2029/0409
摘要： Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.
摘要翻译： 公开了用于确定存储器的通过/失败状态的装置和方法。 在至少一个实施例中，对于与页面相对应的每个页面缓冲器等级的一组公共线路确定所有连接的存储器单元的通过/失败状态，并且可以将每行的通过/失败状态结果组合 确定内存页面的通过/失败。
-
公开(公告)号：US08472256B2
公开(公告)日：2013-06-25
申请号：US12778838
申请日：2010-05-12
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described.
-
公开(公告)号：US08369157B2
公开(公告)日：2013-02-05
申请号：US13039778
申请日：2011-03-03
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/3454
摘要： Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.
-
公开(公告)号：US08358538B2
公开(公告)日：2013-01-22
申请号：US13268158
申请日：2011-10-07
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 存储器件，用于根据存储在存储器件中的擦除操作周期计数值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
-
-
-
-
-
-
-
-
-
搜索结果
147 条记录 (耗时 0.027 秒)
