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公开(公告)号：US06897535B2
公开(公告)日：2005-05-24
申请号：US10438689
申请日：2003-05-14
IPC分类号： H01L23/58 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/573 , H01L27/02 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness is disposed among said plurality of layers to thereby render the integrated circuit structure intentionally inoperable.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓和受控厚度的多层材料形成。 在所述多个层之间设置受控厚度的介电材料层，从而使集成电路结构有意无法操作。
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42.发明授权Implanted hidden interconnections in a semiconductor device for preventing reverse engineering 失效在半导体器件中隐藏的互连用于防止逆向工程公开(公告)号：US06815816B1
公开(公告)日：2004-11-09
申请号：US09696826
申请日：2000-10-25
IPC分类号： H01L2348
CPC分类号： H01L27/02 , H01L21/743
摘要： A camouflaged interconnection for interconnecting two spaced-apart implanted regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first implanted region forming a conducting channel between the two spaced-apart implanted regions, the conducting channel being of the same common conductivity type and bridging a region between the two spaced-apart regions, and a second implanted region of opposite conductivity to type, the second implanted region being disposed between the two spaced-apart implanted regions of common conductivity type and over lying the conducting channel to camouflage the conducting channel from reverse engineering.
摘要翻译： 一种用于在集成电路或器件中互连公共导电类型的两个间隔开的注入区域的伪装互连和其形成方法。 伪装的互连包括在两个间隔开的注入区之间形成导电沟道的第一注入区，导电沟具有相同的共同导电类型并桥接两个间隔开的区之间的区域， 导电类型，第二注入区域设置在两个间隔开的公共导电类型的注入区域之间，并且躺在导电沟道上以伪造导电沟道以进行逆向工程。
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公开(公告)号：US06613661B1
公开(公告)日：2003-09-02
申请号：US09607009
申请日：2000-06-29
IPC分类号： H01L2144
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is protected from reverse engineering by connecting doped circuit elements of like conductivity with a doped implant in the substrate, rather than with a metallized interconnect. The doped circuit elements and their corresponding implant interconnections can be formed in a common fabrication step with common implant masks, such that they have an integral structure with similar dopant concentrations. The metallization above the substrate surface can be designed to provide further masking of the interconnects, and microbridges can be added to span strips of transistor gate material in the interconnect path.
摘要翻译： 通过将类似导电性的掺杂电路元件与衬底中的掺杂注入相连而不是金属化互连来保护集成电路免于逆向工程。 掺杂电路元件及其对应的注入互连可以在具有公共注入掩模的公共制造步骤中形成，使得它们具有类似掺杂剂浓度的整体结构。 衬底表面之上的金属化可被设计成提供互连的进一步屏蔽，并且微桥可以被添加到在互连路径中跨越晶体管栅极材料的条带。
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44.发明授权Memory with a bit line block and/or a word line block for preventing reverse engineering 有权具有位线块和/或字线块的存储器用于防止逆向工程公开(公告)号：US06459629B1
公开(公告)日：2002-10-01
申请号：US09848564
申请日：2001-05-03
IPC分类号： G11C700
摘要： A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling a data line associated with the at least one memory cell to a constant voltage source in response to the switch or link assuming an open state.
摘要翻译： 一种用于阻止未经授权的访问半导体存储器中的至少一个存储单元的方法和电路。 该方法包括提供在要阻止对至少一个存储器单元的访问时呈现打开状态的开关和/或链接; 以及响应于所述开关或链路假定为打开状态，将与所述至少一个存储器单元相关联的数据线耦合到恒定电压源。
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45.发明授权Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering 有权具有晶体管几何形状和通道的数字电路停止提供防止逆向工程的伪装
公开(公告)号：US06064110A
公开(公告)日：2000-05-16
申请号：US243855
申请日：1999-02-03
IPC分类号： H01L21/3205 , G06F21/06 , G11C7/24 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/02 , H01L27/04 , H01L23/58
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002
摘要： An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.
摘要翻译： 通过制造具有共同尺寸和几何布局的所有具有类似导电性的晶体管来保护集成数字电路免受逆向工程，为不同的逻辑单元提供通用布局，将类似导电性的掺杂电路元件与衬底中的导电掺杂植入物连接起来，而不是 金属化互连，并且提供由不可识别的通道停止中断的非功能性视在互连，使得所有单元看起来具有共同的互连方案。 通过在晶体管阵列上提供均匀的金属引线图案来增强伪装，晶体管具有均匀的重掺杂注入阱图案，用于连接到引线; 通道停止阻塞不需要的抽头引线连接。
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公开(公告)号：US5973375A
公开(公告)日：1999-10-26
申请号：US869524
申请日：1997-06-06
CPC分类号： H01L21/743 , H01L27/02 , H01L2924/0002
摘要： Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two implanted regions is camouflaged by implanting a conductive buried layer of the same doping conductivity as the implanted regions when a connection is desired, and a field implant of opposite conductivity to the implanted regions when no connection is desired, and forming steps into the substrate at the boundaries of the buried layer or field implant that mask the steps formed between different conductivity regions during a selective etch by a reverse engineer. The masking steps are preferably formed by field oxide layers that terminate at the boundaries of the buried layers and field implants.
摘要翻译： 半导体衬底中的注入区域（例如相邻晶体管的源极或漏极）之间的连接通过掩埋导电植入而不是上层金属化而制成。 当需要连接时，通过注入与注入区相同的掺杂电导率的导电掩埋层和当不需要连接时与注入区相反的导电性的场注入来伪装两个注入区之间的连接的存在或不存在 ，并且在掩模层或场注入的边界处，在通过反向工程师进行选择性蚀刻期间掩蔽形成在不同导电区域之间的步骤的步骤，形成步骤。 掩蔽步骤优选由终止于掩埋层和场植入物的边界的场氧化物层形成。
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公开(公告)号：US4556798A
公开(公告)日：1985-12-03
申请号：US512879
申请日：1983-07-12
IPC分类号： H01J37/317 , H01J37/30 , H01J37/305 , H01L21/027 , H01L21/30
CPC分类号： H01J37/3007
摘要： Two lens focused ion beam column (10) has an accelerating lens (20) which carries a potential to focus an image of the liquid metal ion source (14) on the mass analyzer slit (26) with a magnification of about unity. Munro lens (36) accelerates the beam of selected ion species and demagnifies the image through a long working distance to provide an ion writing spot of less than about 1000 .ANG. size.
摘要翻译： 两个透镜聚焦离子束柱（10）具有加速透镜（20），该加速透镜具有将液体金属离子源（14）的图像以大致一致的放大率聚焦在质量分析器狭缝（26）上的潜力。 Munro透镜（36）加速选定离子种类的光束，并通过长工作距离使图像缩小，以提供小于约1000 ANGSTROM大小的离子写入点。
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