公开(公告)号：US20120008388A1

公开(公告)日：2012-01-12

申请号：US12834233

申请日：2010-07-12

申请人： YAO-WEN CHANG ,  Tao-Cheng Lu

发明人： YAO-WEN CHANG ,  Tao-Cheng Lu

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404

摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group and the secondary voltage distribution groups includes N threshold-voltage distribution curves, and N is an integer greater than 2; selecting a first operation level and a second operation level according to a programming command; programming the first storage position according to the threshold-voltage distribution curve corresponding to the first operation level in the main voltage distribution group; selecting one of the secondary voltage distribution groups according to the first operation level and programming the second storage position according to the threshold-voltage distribution curve corresponding to the second operation level in the selected secondary voltage distribution group.

摘要翻译： 提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。 操作方法包括：设置主电压分配组和多个次级电压分布组，其中主电压分配组和次级电压分配组中的每一个包括N个阈值电压分布曲线，并且N是大于2的整数 ; 根据编程命令选择第一操作级别和第二操作级别; 根据与主电压分配组中的第一操作电平相对应的阈值电压分布曲线对第一存储位置进行编程; 根据第一操作电平选择二次电压分配组中的一个，并根据与所选次级电压分配组中的第二操作电平对应的阈值电压分布曲线对第二存储位置进行编程。

公开(公告)号：US06756638B2

公开(公告)日：2004-06-29

申请号：US10033748

申请日：2001-12-19

申请人： Yao Wen Chang ,  Tao-Cheng Lu

发明人： Yao Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L2701

CPC分类号： H01L29/1033 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/7835

摘要： A MOSFET structure comprises a tortuous gate having a first sidewall and a second sidewall, disposed over a semiconductor substrate. A source region is disposed within the semiconductor substrate adjacent to the first sidewall of the tortuous gate. The source region comprises a broader part and a narrower part. Contacts are positioned above the broader part of the source region and are in contact with the broader part of the source region. A drain region is disposed within the semiconductor substrate adjacent to the second sidewall of the tortuous gate. The drain region comprises a broader part and a narrower part. Contacts are disposed above the broader part of the drain region and are in contact with the broader part of the drain region. The broader part of the drain region is disposed opposite to the narrower part of the source region. The narrower part of the drain region is disposed opposite to the broader part of the source region.

摘要翻译： MOSFET结构包括设置在半导体衬底上的具有第一侧壁和第二侧壁的曲折栅极。 源极区域设置在与弯曲栅极的第一侧壁相邻的半导体衬底内。 源区域包括较宽部分和较窄部分。 触点位于源极区域的较宽部分上方并与源区域的较宽部分接触。 漏极区域设置在与曲折栅极的第二侧壁相邻的半导体衬底内。 漏极区域包括较宽部分和较窄部分。 触点设置在漏极区域的较宽部分上方并与漏极区域的较宽部分接触。 漏极区域的较宽部分设置成与源极区域的较窄部分相对。 漏极区域的较窄部分设置成与源极区域的较宽部分相对。

公开(公告)号：US07291870B2

公开(公告)日：2007-11-06

申请号：US10904475

申请日：2004-11-12

申请人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266 ,  H01L29/7436 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

摘要翻译： 耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

公开(公告)号：US20070159893A1

公开(公告)日：2007-07-12

申请号：US11616770

申请日：2006-12-27

申请人： TSO-HUNG FAN ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： TSO-HUNG FAN ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。

公开(公告)号：US07187527B2

公开(公告)日：2007-03-06

申请号：US10933181

申请日：2004-09-02

申请人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.

摘要翻译： 用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。 有源P环围绕具有与半导体衬底相同的导电类型的导电区域的晶体管的源极和漏极。 耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。 偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

公开(公告)号：US07031196B2

公开(公告)日：2006-04-18

申请号：US10757073

申请日：2004-01-14

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/00

CPC分类号： G11C16/0475 ,  G11C16/3468 ,  H01L21/28273 ,  H01L29/792 ,  H01L29/7923

摘要： A method of programming the memory cell comprises setting the memory cell to an initial state of a first gate threshold voltage, performing a processing sequence including: applying a voltage bias between the gate and the first junction region to cause electric hole to migrate towards and be retained in the trapping layer, and evaluating a read current generated in response to the voltage bias to determine whether a second gate threshold voltage is reached, wherein the second gate threshold voltage is lower than the first gate threshold voltage. The processing sequence is repeated a number of times by varying one or more time the voltage bias between the gate and the first junction region until the second gate threshold voltage is reached and the memory cell is in a program state.

摘要翻译： 一种对存储器单元进行编程的方法包括将存储单元设置为第一栅极阈值电压的初始状态，执行处理顺序，包括：在栅极与第一结区域之间施加电压偏置，使电孔朝向 保持在捕获层中，并且评估响应于电压偏置产生的读取电流，以确定是否达到第二栅极阈值电压，其中第二栅极阈值电压低于第一栅极阈值电压。 通过改变栅极和第一结区域之间的电压偏压的一个或多个时间直到达到第二栅极阈值电压并且存储器单元处于编程状态来重复处理顺序多次。

公开(公告)号：US06917073B2

公开(公告)日：2005-07-12

申请号：US10643877

申请日：2003-08-20

申请人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115

摘要： To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

摘要翻译： 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US06914819B2

公开(公告)日：2005-07-05

申请号：US10653892

申请日：2003-09-04

申请人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Hung-Yueh Chen ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of operating a non-volatile memory cell, wherein the non-volatile memory cell includes a word line, a first bit line, and a second bit line, the method includes programming the memory cell that includes applying a high positive bias to the first bit line, applying a ground bias to the second bit line, and applying a high negative bias to the word line, wherein positively-charged holes tunnel through the dielectric layer into the trapping layer.

摘要翻译： 一种操作非易失性存储单元的方法，其中所述非易失性存储单元包括字线，第一位线和第二位线，所述方法包括对所述存储器单元进行编程，所述存储单元包括向所述存储单元施加高正偏压 第一位线，对第二位线施加接地偏置，以及向字线施加高负偏压，其中带正电荷的空穴穿过介电层进入捕获层。

公开(公告)号：US20050040458A1

公开(公告)日：2005-02-24

申请号：US10643877

申请日：2003-08-20

申请人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115

摘要： To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

摘要翻译： 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US06801453B2

公开(公告)日：2004-10-05

申请号：US10112871

申请日：2002-04-02

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/26

摘要： A method of a read scheme for a non-volatile memory cell. The non-volatile memory cell includes a substrate, a source, a drain and a gate above a channel separated by a nonconducting charge trapping material sandwiched between first and second insulating layers. The method applies a first positive drain-to-source bias, a second positive source-to-substrate bias, and a third positive gate-to-source bias to read the source-side charges trapped in the trapping material near the source side.

摘要翻译： 一种用于非易失性存储单元的读取方案的方法。 非易失性存储单元包括衬底，源极，漏极以及由夹在第一绝缘层和第二绝缘层之间的非导电电荷捕获材料隔开的沟道之上的栅极。 该方法应用第一正的漏极 - 源极偏置，第二正的源极 - 衬底偏置和第三正向栅极 - 源偏置来读取在源极附近的捕获材料中的源极电荷。