公开(公告)号：US20100033884A1

公开(公告)日：2010-02-11

申请号：US12186400

申请日：2008-08-05

申请人： Tso-Hung Fan ,  Kuo-Ji Chen

发明人： Tso-Hung Fan ,  Kuo-Ji Chen

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： This invention discloses a trigger circuit for an electrostatic discharge (ESD) protection device, the ESD protection device being turned on during an ESD event and being turned off during a normal operation, the trigger circuit comprises a voltage sensing circuit coupled to a bonding pad, the voltage sensing circuit being configured to produce a first predetermined voltage during a ESD event, and to produce a second predetermined voltage complimentary to the first predetermined voltage during a normal operation, and a voltage converting circuit having a positive feedback circuit and coupled between the voltage sensing circuit and the ESD protection device for converting the first predetermined voltage to a third predetermined voltage for turning on the ESD protection device, and for converting the second predetermined voltage to a fourth predetermined voltage for turning off the ESD protection device.

摘要翻译： 本发明公开了一种用于静电放电（ESD）保护装置的触发电路，ESD保护装置在ESD事件期间被接通并且在正常操作期间被断开，触发电路包括耦合到接合焊盘的电压感测电路， 电压感测电路被配置为在ESD事件期间产生第一预定电压，并且在正常操作期间产生与第一预定电压互补的第二预定电压，以及电压转换电路，具有正反馈电路并耦合在电压 感测电路和用于将第一预定电压转换为用于接通ESD保护装置的第三预定电压的ESD保护装置，以及用于将第二预定电压转换为用于关闭ESD保护装置的第四预定电压。

公开(公告)号：US06790730B2

公开(公告)日：2004-09-14

申请号：US10156325

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11253 ,  H01L21/26586 ,  H01L27/112

摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

摘要翻译： 描述了一种用于掩模只读存储器件的制造方法。 该方法提供衬底，并且在衬底上形成掺杂导电层。 之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。 多个扩散区同时形成在基板中的棒状导电层的下方。 在电介质层上进一步形成图案化的导电层。

公开(公告)号：US06706575B2

公开(公告)日：2004-03-16

申请号：US10055265

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/115

摘要： A method for fabricating a non-volatile memory is described. A substrate having a strip stacked structure thereon is provided. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A silicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the silicon layer and the strip stacked structure are then patterned successively in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate and the silicon layer. Thereafter, the cap layer is removed and a metal salicide layer is formed on the exposed surface of the silicon layer.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有条带堆叠结构的基板。 然后在衬底旁边的衬底上形成掩埋漏极，并在掩埋漏极上形成绝缘层。 在衬底上顺序形成硅层和覆盖层。 然后，在垂直于埋地漏极的方向上连续地对盖层，硅层和条带堆叠结构进行图案化，其中条带层叠结构被图案化成多个栅极。 衬底氧化物层形成在栅极，衬底和硅层的暴露表面上。 此后，除去盖层，并在硅层的暴露表面上形成金属硅化物层。

公开(公告)号：US06665212B1

公开(公告)日：2003-12-16

申请号：US10065032

申请日：2002-09-12

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C11/5621 ,  G11C16/30 ,  G11C2211/5634

摘要： The reference current generation circuit of a multiple bit flash memory. An identical boosted word-line voltage is applied to the gate terminal of reference memory cells in different reference current generation units and a different substrate voltage is applied to the substrate of each reference memory cell so that different reference currents are produced. This arrangement reduces different degree of shifting in the reference currents due to temperature and source voltage Vcc variation.

摘要翻译： 多位闪存的参考电流产生电路。 将相同的升压字线电压施加到不同参考电流产生单元中的参考存储器单元的栅极端子，并且将不同的衬底电压施加到每个参考存储器单元的衬底，使得产生不同的参考电流。 这种布置降低了由于温度和源电压Vcc变化引起的参考电流的不同移位程度。

公开(公告)号：US06607957B1

公开(公告)日：2003-08-19

申请号：US10064614

申请日：2002-07-31

申请人： Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L218246

CPC分类号： H01L27/11568 ,  H01L21/28282

摘要： The present invention relates to a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, defining the doped polysilicon layer by using a patterned mask layer to form a plurality of doped polysilicon lines and expose a portion of the substrate. Afterwards, a thermal process is performed to form an oxide layer on the exposed substrate and sidewalls of the doped polysilicon lines. During the thermal process, the dopants are driven into the substrate to form a source/drain region, thus obtaining a plurality of bit lines including the doped polysilicon lines and the source/drain region. Following removal of the patterned mask layer, a self-aligned silicide layer is formed on the top surface of the bit lines. After removing the oxide layer, a silicon nitride stacked layer and a plurality of word lines are formed over the substrate.

摘要翻译： 本发明涉及一种用于制造氮化物只读存储器（NROM）的方法，包括：在衬底上形成掺杂多晶硅层，通过使用图案化掩模层来形成掺杂多晶硅层，以形成多个掺杂多晶硅线并暴露 衬底的一部分。 之后，进行热处理以在暴露的衬底和掺杂多晶硅线的侧壁上形成氧化物层。 在热处理期间，掺杂剂被驱动到衬底中以形成源极/漏极区域，从而获得包括掺杂多晶硅线路和源极/漏极区域的多个位线。 在去除图案化掩模层之后，在位线的顶表面上形成自对准的硅化物层。 在除去氧化物层之后，在衬底上形成氮化硅层叠层和多条字线。

公开(公告)号：US07002849B2

公开(公告)日：2006-02-21

申请号：US10983019

申请日：2004-11-05

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C5/06 ,  G06F12/00

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

公开(公告)号：US20050270844A1

公开(公告)日：2005-12-08

申请号：US11198684

申请日：2005-08-04

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

公开(公告)号：US20050082597A1

公开(公告)日：2005-04-21

申请号：US10983019

申请日：2004-11-05

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

摘要翻译： 描述了用氮化物隧穿层编程和擦除非易失性存储器的方法。 非易失性存储器通过向栅极施加第一电压并使衬底接地以接通源极和漏极之间的沟道并且向漏极施加第二电压并且将源接地以感应通道中的电流来编程 从而在其中产生热电子。 热电子通过氮化物隧穿层注入到非挥发性的电荷捕获层中并被捕获在其中。 通过向漏极施加第一正偏压，向栅极施加第二正偏压，并且将源极和衬底接地以在沟道区域中产生热电子空穴来擦除非易失性存储器。 热电子空穴通过氮化物隧穿层注入电荷捕获层。

公开(公告)号：US06785163B2

公开(公告)日：2004-08-31

申请号：US10387501

申请日：2003-03-14

申请人： Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C29/028 ,  G11C16/04 ,  G11C16/28 ,  G11C2029/5006

摘要： A trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

摘要翻译： 一种微调电路和方法，用于调整闪速存储器中的参考单元的电流电平，该闪存存储器包括读出放大器，用于比较来自其栅极接收字线信号电压的存储单元的单元电流与参考电流的参考电流， 接收由分压器划分字线信号电压而产生的偏压，从而产生感测信号。 分压器至少包括可编程闪存单元，用作可变电阻器，其电阻通过编程/擦除电路参考存储器单元的编程对可编程闪存单元进行编程来确定。

公开(公告)号：US06709921B2

公开(公告)日：2004-03-23

申请号：US09967717

申请日：2001-09-27

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

摘要翻译： 描述了具有分离浮动栅极的闪速存储器件的制造方法。 该方法提供了一种衬底，其中氧化物层和图案化的牺牲层依次形成在衬底上。 然后使用图案化的牺牲层作为掩模，进行离子注入，以在图案化牺牲层的侧面旁边的衬底中形成具有轻掺杂的源/漏区的源/漏区。 进一步进行各向同性蚀刻以去除图案化牺牲层的一部分，然后在图案化牺牲层的侧壁上形成两个导电间隔物。 然后去除由两个导电间隔物暴露的图案化牺牲层和氧化物层以形成两个浮动栅极。 随后，在基板上形成电介质层和控制栅极。