摘要:
Integrated circuits with multi-dimensional pad structures are provided. An exemplary embodiment of an integrated circuit device with multi-dimensional pad structures comprises an integrated circuit (IC) stack structure comprising a plurality of device layers, wherein one of the devices comprise a first pad exposed by an edge surface thereof.
摘要:
A method of monitoring uniformity of a wafer is provided. A wafer parameter is selected. Manufacturing data is collected. The manufacturing data includes measurements of the selected wafer parameter. An average offset profile of the wafer parameter for a first and second wafer is determined using the manufacturing data. The first and second wafer are associated with a product type and were processed by a processing tool. An offset profile for a third wafer is predicted for a wafer using the average offset profile. The third wafer is associated with the product type and was processed by the processing tool.
摘要:
A method of forming a metal feature in a low-k dielectric layer is provided. The method includes forming an opening in a low-k dielectric layer, forming a metal layer having a substantially planar surface over the low-k dielectric layer using spin-on method, and stress free polishing the metal layer. Preferably, the metal layer comprises copper or copper alloys. The metal layer preferably includes a first sub layer having a substantially non-planar surface and a second sub layer having a substantially planar surface on the first sub layer.
摘要:
A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof.
摘要:
Integrated circuits with multi-dimensional pad structures are provided. An exemplary embodiment of an integrated circuit device with multi-dimensional pad structures comprises an integrated circuit (IC) stack structure comprising a plurality of device layers, wherein one of the devices comprise a first pad exposed by an edge surface thereof.
摘要:
A method for forming a damascene structure by providing a single process solution for resist ashing while avoiding and repairing plasma etching damage as well as removing absorbed moisture in the dielectric layer, the method including providing a substrate comprising an uppermost photoresist layer and an opening extending through a thickness of an inter-metal dielectric (IMD) layer to expose an underlying metal region; and, carrying out at least one supercritical fluid treatment comprising supercritical CO2, a first co-solvent, and an additive selected from the group consisting of a metal corrosion inhibitor and a metal anti-oxidation agent to remove the uppermost photoresist layer, as well as including an optional dielectric insulating layer bond forming agent.
摘要:
The preferred embodiments of the present invention provide a three-dimensional (3D) semiconductor structure and a method of forming the same. The 3D semiconductor structure includes a first substrate bonded to a second substrate. The first substrate includes substantially all NMOS devices. The second substrate includes substantially all PMOS devices. The substrates can be bonded face-to-face, face-to-back, or back-to-back. The method includes providing a first substrate and a second substrate, forming a first circuit comprising at least one NMOS device on the first substrate, wherein the first substrate includes substantially no PMOS devices, forming a second circuit comprising at least one PMOS device on the second substrate, wherein the second substrate includes substantially no NMOS devices, and bonding the first and second substrates after forming the first and second circuits.
摘要:
A planarizing method for forming a patterned planarized aperture fill layer within an aperture employs a planarizing stop layer formed of a reductant based material, such as but not limited to a hydrogenated silicon nitride material. The reductant based material provides the planarizing stop layer with enhanced planarizing stop properties. The method is particularly useful within the context of CMP planarizing methods.
摘要:
A method for treating an inter-metal dielectric (IMD) layer to improve a mechanical strength and/or repair plasma etching damage including providing a low-K silicon oxide containing dielectric insulating layer; and carrying out a super critical fluid treatment of the low-K dielectric insulating layer including supercritical CO2 and a solvent including a silicon bond forming substituent having a bonding energy greater than a Si—H to replace at least a portion of the Si—H bonds with the silicon bond forming substituent.
摘要:
A planarizing method for forming a patterned planarized aperture fill layer within an aperture employs a planarizing stop layer formed of a reductant based material, such as but not limited to a hydrogenated silicon nitride material. The reductant based material provides the planarizing stop layer with enhanced planarizing stop properties. The method is particularly useful within the context of CMP planarizing methods.