公开(公告)号：US06232646B1

公开(公告)日：2001-05-15

申请号：US09082607

申请日：1998-05-20

申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

IPC分类号： H01L2900

CPC分类号： H01L21/7621 ,  H01L21/76232

摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

公开(公告)号：US6146944A

公开(公告)日：2000-11-14

申请号：US39783

申请日：1998-03-16

申请人： Yue-Song He ,  Che-Hoo Ng ,  Pau-Ling Chen

发明人： Yue-Song He ,  Che-Hoo Ng ,  Pau-Ling Chen

IPC分类号： H01L21/265 ,  H01L21/8247

CPC分类号： H01L27/11517 ,  H01L21/26586

摘要： A P-type dopant is implanted into a substrate region 94 under a select drain gate transistor field oxide region 75 at a large tilt angle .alpha., to prevent field turn-on under the select drain gate transistor field oxide region 75 in a non-volatile memory device such as a NAND flash memory device. A substrate region 114 under a select source gate transistor field oxide region 77 can also be implanted with a P-type dopant to prevent field turn-on under the region 77 if select source gates 90 and 92 are to be supplied with a voltage in operation rather than grounded. The substrate regions 94 and 114 under both the select drain gate transistor field oxide region 75 and the select source gate transistor field oxide region 77 can be implanted with the P-type dopant using a fixed-angle ion beam 120, by rotating the wafer 124 between the step of implanting one of the substrate regions and the step of implanting the other region.

摘要翻译： P型掺杂剂以大的倾斜角α被注入到选择漏极栅极晶体管场氧化物区域75下方的衬底区域94中，以防止选择漏极栅极晶体管场氧化物区域75在非易失性 诸如NAND闪存器件的存储器件。 选择源栅极晶体管场氧化物区域77下方的衬底区域114也可以注入P型掺杂剂，以防止在选择源极栅极90和92被施加电压时在区域77下的场导通 而不是接地。 在选择漏极栅极晶体管场氧化物区域75和选择源极栅极晶体管场氧化物区域77两者之下的衬底区域94和114可以使用固定角度离子束120注入P型掺杂剂，通过旋转晶片124 在植入一个衬底区域的步骤和植入另一个区域的步骤之间。

公开(公告)号：US6020238A

公开(公告)日：2000-02-01

申请号：US978107

申请日：1997-11-25

申请人： Yue-Song He ,  Effiong Ibok

发明人： Yue-Song He ,  Effiong Ibok

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L21/28273

摘要： A method of fabricating an interpolysilicon dielectric structure in a non-volatile memory includes the steps of forming a nitride layer 12 on a floating gate 10 and a high dielectric constant layer 14 on the nitride layer 12. A control gate 18 may be formed directly on the high dielectric constant layer 14, or on a thin layer 16 of an oxide or an oxynitride on the high dielectric constant layer 14.

摘要翻译： 在非易失性存储器中制造多晶硅介质结构的方法包括在氮化物层12上的浮置栅极10和高介电常数层14上形成氮化物层12的步骤。控制栅极18可直接形成在 高介电常数层14或在高介电常数层14上的氧化物或氧氮化物的薄层16上。

公开(公告)号：US5940718A

公开(公告)日：1999-08-17

申请号：US119715

申请日：1998-07-20

申请人： Effiong Ibok ,  Yue-Song He ,  Yowjuang W. Liu

发明人： Effiong Ibok ,  Yue-Song He ,  Yowjuang W. Liu

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： A method for fabricating a semiconductor device including a silicon substrate and plural silicon stacks thereon includes forming a nitride shield layer on the substrate and stacks to cover the stacks, such that the stacks are protected from loss of critical dimension during subsequent isolation trench formation and oxidation. In other words, the edge of each stack, and thus the critical dimension of the silicon layers of the stack, is protected from oxidation by the nitride shield layer.

摘要翻译： 一种用于制造包括硅衬底和其上的多个硅堆叠的半导体器件的方法包括在衬底上形成氮化物屏蔽层并堆叠以覆盖堆叠，使得在随后的隔离沟槽形成和氧化期间保护堆叠免受临界尺寸的损失 。 换句话说，每个堆叠的边缘以及因此堆叠的硅层的临界尺寸被氮化物屏蔽层防止氧化。

公开(公告)号：US08330189B2

公开(公告)日：2012-12-11

申请号：US12819566

申请日：2010-06-21

申请人： Harry S. Luan ,  Yue-Song He ,  Ting-Wah Wong

发明人： Harry S. Luan ,  Yue-Song He ,  Ting-Wah Wong

IPC分类号： H01L23/535

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

摘要翻译： 由金属绝缘体半导体电池形成的一次可编程非易失性存储器。 电池处于形成在半导体衬底中的导电栅极线和交叉掺杂半导体线的交叉点。

公开(公告)号：US07808032B2

公开(公告)日：2010-10-05

申请号：US12145681

申请日：2008-06-25

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7854 ,  H01L29/7881

摘要： A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

摘要翻译： 浮动栅极存储单元的沟道区域（104）至少部分地位于半导体衬底的鳍状突起（110P）中。 浮栅的顶面可以沿着突起的至少两侧下降到突起的顶部（110P-T）的下方。 控制门的底面也可能下降至低于突起顶部的水平。 浮动门的底面可能下降到突起顶部以下至少50％的高度。 将浮动栅极与突起分离的电介质（120）可以在突起的顶部处至少与在突起的顶部下方的突起高度的至少50％的水平（L2）相同。 存储器和非存储器集成电路中的非常狭窄的鳍或其他窄特征可以通过提供第一层（320）然后从第二层形成间隔物（330）而形成，而不需要在由第一层制成的特征的侧壁上进行光刻。 然后在相邻间隔物之间​​的区域中形成窄鳍片或其它特征，而无需进一步的光刻。 更具体地，在这些区域中形成第三层（340），并且第一层和间隔物被选择性地去除到第三层。 第三层用作掩模以形成窄特征。

公开(公告)号：US20090101961A1

公开(公告)日：2009-04-23

申请号：US11876557

申请日：2007-10-22

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： The present disclosure provides a memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, a tantalum-nitride layer, and a control gate layer. When a positive bias is applied to the control gate and the select gate, negative charges are injected from a channel region of a substrate through the tunneling dielectric layer and into the charge storage layer to thereby store the negative charges in the charge storage layer. When a negative bias is applied to the control gate, negative charges are tunneled from the charge storage layer to the channel region of the substrate through the tunneling dielectric layer.

摘要翻译： 本公开提供了一种存储器件，其具有与单元堆叠相邻形成的单元堆叠和选择栅极。 电池堆包括隧道介电层，电荷存储层，阻挡介电层，氮化钽层和控制栅层。 当向控制栅极和选择栅极施加正偏压时，从衬底的沟道区域通过隧道电介质层注入负电荷并进入电荷存储层，从而将负电荷存储在电荷存储层中。 当向控制栅极施加负偏压时，负电荷通过隧道电介质层从电荷存储层隧穿到衬底的沟道区。

公开(公告)号：US07511333B2

公开(公告)日：2009-03-31

申请号：US11246447

申请日：2005-10-06

申请人： Yue-Song He ,  Chung Wai Leung ,  Jin-Ho Kim ,  Kwok Kwok Ng

发明人： Yue-Song He ,  Chung Wai Leung ,  Jin-Ho Kim ,  Kwok Kwok Ng

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L29/42336 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

摘要： A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.

摘要翻译： 存储单元（110）具有多个浮动栅极（120L，120R）。 沟道区域（170）包括与相应浮动栅极相邻的多个子区域（220L，220R），以及浮置栅极之间的连接区域（210）。 连接区域具有与源极/漏极区域（160）相同的导电类型以增加沟道导电性。 因此，即使栅极间电介质（144）在浮置栅极之间变厚，削弱了沟道中的控制栅极（104）电场，浮动栅极也可以更靠近在一起。

公开(公告)号：US07084458B1

公开(公告)日：2006-08-01

申请号：US11120690

申请日：2005-05-02

申请人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

发明人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L29/66598

摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

摘要翻译： 公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。 这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。 此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

公开(公告)号：US07020021B1

公开(公告)日：2006-03-28

申请号：US10981833

申请日：2004-11-04

申请人： Wing-Han Leung ,  Richard M. Fastow ,  Yue-Song He ,  Sheung-Hee Park

发明人： Wing-Han Leung ,  Richard M. Fastow ,  Yue-Song He ,  Sheung-Hee Park

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3445 ,  G11C16/3468 ,  G11C16/3477

摘要： A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.

摘要翻译： 描述了擦除多级单元闪存阵列中的位的方法。 该方法包括在每个擦除脉冲之后应用过擦除验证。 如果电池验证为过擦除，则施加斜坡过擦除校正脉冲。 每个过擦除校正脉冲的电压递增地大于先前的脉冲，直到所有单元中的所有位通过过擦除验证。 以这种方式，擦除位的阈值电压分布的宽度保持最小。